Memory device and repair method of the memory device

A memory device comprising:

• a first cell region provided in a first physical layer among a plurality of stacked physical layers of the memory device, the first cell region comprising a first bit line and a first redundant bit line;
• a second cell region provided in a second physical layer among the plurality of stacked physical layers, the second cell region comprising a second bit line and a second redundant bit line;
• a peripheral region provided in a third physical layer among the plurality of stacked physical layers, the peripheral region comprising a plurality of first page buffers configured to be respectively connected to the first bit line and the second bit line, and a second page buffer configured to be commonly connected to the first redundant bit line and the second redundant bit line;
• and
• a control circuit configured to:
• based on the first bit line being identified as defective, replace the first bit line with the first redundant bit line;
• and
• based on the second bit line being identified as defective, replace the second bit line with the second redundant bit line,
• wherein the first redundant bit line and the second redundant bit line share the second page buffer.