Semiconductor device with selective command delay and associated methods and systems

A memory system, comprising:

• one or more memories storing instructions;
• and
• one or more processors coupled with the one or more memories and individually or collectively operable to execute the instructions to cause the memory system to:
• obtain a duration for a delay during an initialization of a memory device of the memory system;
• obtain, via a mode register of the memory device of the memory system, an indication of a mode in which one or more commands are associated with the delay;
• receive a command at the memory device while the memory device is operated in the mode;
• and
• execute the command at the memory device after the delay in accordance with the mode in which the one or more commands are associated with the delay, wherein executing the command after the delay is based at least in part on obtaining the duration for the delay.

A memory system, comprising:

• processing circuitry associated with one or more memory devices and configured to cause the memory system to:
• obtain a duration for a delay during an initialization of a memory device of the one or more memory devices;
• obtain, via a mode register of the memory device, an indication of a mode in which one or more commands are associated with the delay;
• receive a command while the memory device is operated in the mode;
• and
• execute the command at the memory device after the delay in accordance with the mode in which the one or more commands are associated with the delay, wherein executing the command after the delay is based at least in part on obtaining the duration for the delay.