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US 12,651,636 B2Granted
Nonvolatile semiconductor memory device
AssigneeKioxia Corporation
InventorTakashi Maeda
Life of this patent
Estimating the term…
Abstract
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.
Claims27
A memory device, comprising:
- a plurality of first memory cells connected in series, the plurality of first memory cells stacked in a first direction;
- a plurality of second memory cells connected in series, the plurality of second memory cells stacked in the first direction;
- a first group of source side select transistors electrically connected to the plurality of first memory cells in series, the first group of source side select transistors including a first transistor and a second transistor connected in series with each other;
- a second group of source side select transistors electrically connected to the plurality of second memory cells in series, the second group of source side select transistors including a third transistor and a fourth transistor connected in series with each other;
- a source line electrically connected to the plurality of first memory cells via the first group of source side select transistors, the source line electrically connected to the plurality of second memory cells via the second group of source side select transistors;
- a plurality of first word lines electrically connected to gates of the plurality of first memory cells, respectively;
- a plurality of second word lines electrically connected to gates of the plurality of second memory cells, respectively;
- a first source side select gate line electrically connected to a gate of the first transistor;
- a second source side select gate line electrically connected to a gate of the second transistor;
- a third source side select gate line electrically connected to a gate of the third transistor;
- and
- a fourth source side select gate line electrically connected to a gate of the fourth transistor, wherein:
- the first source side select gate line and the second source side select gate line are electrically disconnected from each other,
- the third source side select gate line and the fourth source side select gate line are electrically disconnected from each other, and
- the first source side select gate line and the third source side select gate line are electrically connected to each other, and the second source side select gate line and the fourth source side select gate line are electrically disconnected from each other.
12 more elements
A memory device, comprising:
- a plurality of first memory cells connected in series, the plurality of first memory cells stacked in a first direction;
- a plurality of second memory cells connected in series, the plurality of second memory cells stacked in the first direction;
- a first group of drain side select transistors electrically connected to the plurality of first memory cells in series, the first group of drain side select transistors including a first transistor and a second transistor connected in series with each other;
- a second group of drain side select transistors electrically connected to the plurality of second memory cells in series, the second group of drain side select transistors including a third transistor and a fourth transistor connected in series with each other;
- a bit line electrically connected to the plurality of first memory cells via the first group of drain side select transistors, the bit line electrically connected to the plurality of second memory cells via the second group of drain side select transistors;
- a plurality of first word lines electrically connected to gates of the plurality of first memory cells, respectively;
- a plurality of second word lines electrically connected to gates of the plurality of second memory cells, respectively;
- a first drain side select gate line electrically connected to a gate of the first transistor;
- a second drain side select gate line electrically connected to a gate of the second transistor;
- a third drain side select gate line electrically connected to a gate of the third transistor;
- and a fourth drain side select gate line electrically connected to a gate of the fourth transistor, wherein:
- the first drain side select gate line and the second drain side select gate line are electrically disconnected from each other, the third drain side select gate line and the fourth drain side select gate line are electrically disconnected from each other, the first drain side select gate line and the third drain side select gate line are electrically connected to each other, and
- wherein the second drain side select gate line and the fourth drain side select gate line are electrically disconnected from each other.
10 more elements
A memory device, comprising:
- a plurality of first memory cells connected in series, the plurality of first memory cells stacked in a first direction;
- a plurality of second memory cells connected in series, the plurality of second memory cells stacked in the first direction;
- a first select transistor and a second select transistor electrically connected to the plurality of first memory cells in series;
- a third select transistor and a fourth select transistor electrically connected to the plurality of second memory cells in series;
- a conductive line electrically connected to the plurality of first memory cells via the first select transistor and the second select transistor,
- the conductive line electrically connected to the plurality of second memory cells via the third select transistor and the fourth select transistor;
- a first gate line electrically connected to a gate of the first select transistor;
- a second gate line electrically connected to a gate of the second select transistor;
- a third gate line electrically connected to a gate of the third select transistor;
- and a fourth gate line electrically connected to a gate of the fourth select transistor
- wherein the first gate line and the third gate line are electrically connected to each other,
- wherein the second gate line and the fourth gate line are electrically disconnected from each other, wherein the first gate line and the second gate line are electrically disconnected from each other, wherein the third gate line and the fourth gate line are electrically disconnected from each other, and
- wherein the conductive line is disposed above a substrate in the first direction.
10 more elements
Dependencies are inferred from the claim text.