Word line booster circuit and method

A memory circuit comprising:

• a control circuit configured to output a plurality of clock pulse signals;
• first and second word line drivers coupled to the control circuit;
• a first input output (I/O) circuit coupled to the control circuit and configured to output first and second pulse signals responsive to the plurality of clock pulse signals;
• a second I/O circuit coupled to the control circuit and configured to output third and fourth pulse signals responsive to the plurality of clock pulse signals;
• a first memory array coupled to the first I/O circuit and the first word line driver;
• a second memory array coupled to the first I/O circuit and the second word line driver;
• a third memory array coupled to the second I/O circuit and the first word line driver;
• a fourth memory array coupled to the second I/O circuit and the second word line driver;
• a first booster circuit coupled to the first I/O circuit and the first and second memory arrays and configured to couple word lines of the first and second memory arrays to a first power supply node responsive to the respective first and second pulse signals and to word line signals on the corresponding word lines;
• and
• a second booster circuit coupled to the second I/O circuit and the third and fourth memory arrays and configured to couple word lines of the third and fourth memory arrays to the first power supply node responsive to the respective third and fourth pulse signals and to word line signals on the corresponding word lines.

A method of operating a memory circuit, the method comprising:

• outputting a plurality of clock pulse signals from a control circuit coupled to first and second word line drivers;
• in response to the plurality of clock pulse signals, outputting first and second pulse signals from a first input output (I/O) circuit coupled to the control circuit and third and fourth pulse signals from a second I/O circuit coupled to the control circuit;
• in response to the respective first and second pulse signals, using a first booster circuit to couple word lines of first and second memory arrays to a power supply node, wherein the first memory array is coupled to the first booster circuit, the first I/O circuit, and the first word line driver, and the second memory array is coupled to the first booster circuit, the first I/O circuit, and the second word line driver;
• and
• in response to the respective third and fourth pulse signals, using a second booster circuit to couple word lines of third and fourth memory arrays to the power supply node, wherein the second memory array is coupled to the second booster circuit, the second I/O circuit, and the first word line driver, and the fourth memory array is coupled to the second booster circuit, the second I/O circuit, and the second word line driver.