Memory device and power-on reading method thereof

A memory device, comprising:

• a controller, being configured to:
• generate a power-on signal according to a voltage level of a power voltage of the memory device;
• respectively detect a plurality of ready states of a plurality of circuits in the memory device sequentially to generate a plurality of ready signals;
• and
• read a plurality of fuse states sequentially to generate a plurality of fuse state signals;
• and
• a shift register circuit, coupled to the controller, the shift register circuit being configured to shift a reference signal sequentially to generate a read pass indication signal according to the power-on signal, the plurality of ready signals and the plurality of fuse state signals by a plurality of shift registers coupled in series,
• wherein each of a plurality of shift registers of the shift register circuit is triggered when the power-on signal, corresponding ready signal or corresponding fuse state signal is at a setting logic value.