Telemetry-capable memory sub-system
AssigneeMicron Technology, Inc.
InventorDavid Andrew Roberts
Life of this patent
Estimating the term…
Abstract
An access counter associated with a segment of a memory device is maintained. The segment comprises a plurality of lines. A first count of the plurality of lines is identified. A subset of the plurality of lines of the segment is monitored. A second count of the subset of the plurality of lines is identified. An access notification for a first line of the subset of the plurality of lines is received. A first value of the access counter is changed by a second value. The second value is weighted based on the first count and the second count. Based on the first value of the access counter, a memory management scheme is implemented.
Claims20
A system comprising:
- a memory device;
- and
- a processing device, operatively coupled to the memory device, to perform operations comprising:
- maintaining an access counter associated with a segment of the memory device, wherein the segment comprises a plurality of lines;
- identifying a first count of the plurality of lines;
- monitoring a subset of the plurality of lines of the segment;
- identifying a second count of the subset of the plurality of lines;
- receiving an access notification for a first line of the subset of the plurality of lines;
- changing a first value of the access counter by a second value, wherein the second value is weighted based on the first count and the second count;
- and
- implementing, based on the first value of the access counter, a memory management scheme.
A method comprising:
- maintaining an access counter associated with a segment of a memory device of a memory sub-system;
- sending, to a host system, a request for ownership of a first line of the segment;
- receiving an access notification for the first line of the segment;
- identifying, in view of a coherency directory associated with memory sub-system, a coherency state of the first line;
- changing a first value of the access counter by a second value, wherein the second value is based on the coherency state of the first line;
- and
- implementing, based on the first value of the access counter, a memory management scheme.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- maintaining an access counter associated with a segment of a memory device, wherein the segment comprises a plurality of lines;
- identifying a first count of the plurality of lines;
- monitoring a subset of the plurality of lines of the segment;
- identifying a second count of the subset of the plurality of lines;
- sending, to a host system, a request for ownership of a first line of the segment;
- receiving an access notification for the first line of the subset of the plurality of lines;
- changing a first value of the access counter by a second value, wherein the second value is based on at least one of an access type of the access notification, a coherency state of the first line, or the first count and the second count;
- and
- implementing, based on the first value of the access counter, a memory management scheme.
Dependencies are inferred from the claim text.