Branch target buffer victim cache
AssigneeMicrosoft Technology Licensing, LLC
InventorsJulio Gago Alonso, Santiago Galan, Antonio Juan Hormigo, Ivan Pizarro
Life of this patent
Estimating the term…
Abstract
Improved branch target buffer (BTB) structures are provided. A device can include branch target buffers storing entries corresponding to branch instructions and corresponding targets of the branch instructions. The device can include a victim cache storing a branch target buffer entry that has been evicted from a branch target buffer of the branch target buffers. The device can include branch prediction circuitry configured to access the victim cache responsive to receiving respective miss indications from each branch target buffer of the branch target buffers.
Claims18
A device comprising:
- branch target buffers storing entries corresponding to branch instructions and corresponding targets of the branch instructions;
- a victim cache storing a branch target buffer entry that has been evicted from a branch target buffer of the branch target buffers;
- and
- branch prediction circuitry configured to access the victim cache only (i) after receiving miss indications from each branch target buffer of the branch target buffers and (ii) if indicator data from at least one branch target buffer of the branch target buffers indicates that an entry for a target of a current entry was previously present in one of the branch target buffers.
A method comprising:
- receiving, at a branch target buffer of branch target buffers, an entry indicating a first program counter value corresponding to a branch instruction and a second program counter value corresponding to an instruction executed immediately after the branch;
- writing, to a victim cache, an entry that has been evicted from a branch target buffer of the branch target buffers;
- receiving miss indications from each branch target buffer of the branch target buffers;
- determining that indicator data from at least one branch target buffer of the branch target buffers indicates that an entry for a target of a current entry was previously present in one of the branch target buffers;
- and
- accessing, by branch prediction circuitry, the victim cache only after (i) receiving miss indications from each branch target buffer of the branch target buffers and (ii) determining the indicator data from at least one branch target buffer of the branch target buffers indicates that an entry for a target of a current entry was previously present in one of the branch target buffers.
A device comprising:
- a program counter configured to generate a program counter value corresponding to an instruction of an application to be executed;
- branch target buffers including entries storing respective program counter values associated with respective branch instructions and respective program counter values that are respective targets of the respective branch instructions, the entries further including indicator data indicating whether an entry for a target of a present entry has been stored in one of the branch target buffers;
- a victim cache configured to receive an entry that has been evicted from a branch target buffer of the branch target buffers;
- and
- branch prediction circuitry configured to access the victim cache only (i) after receiving miss indications from each branch target buffer of the branch target buffers and (ii) if the indicator data from at least one branch target buffer of the branch target buffers indicates that an entry for a target of a current entry was previously present in one of the branch target buffers.
Dependencies are inferred from the claim text.