Circuitry and methods for capability informed prefetches

A method comprising:

• executing, by an execution circuit of a processor, an instruction that generates a memory access request for an element in memory via a first capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a first object to which the first capability authorizes access;
• prefetching, by a prefetch circuit of the processor, an additional element from the memory to a cache of the processor;
• determining, by the processor, if the additional element is a second capability comprising an address field of a second element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a second object to which the second capability authorizes access;
• prefetching, by the prefetch circuit, the second element from the memory to the cache based on the additional element being the second capability;
• and
• further comprising one of:
• determining, by the prefetch circuit, that the additional element is a candidate pointer in a chain of linked pointers, and the prefetching of the additional element from the memory to the cache is based on the additional element being the candidate pointer;
• prefetching, by the prefetch circuit, one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object,
• determining, by the processor, if the one or more further elements is a respective capability comprising an address field of a respective element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a respective object to which the respective capability authorizes access, and
• prefetching, by the prefetch circuit, the respective element from the memory to the cache for each of the one or more further elements that is the respective capability;
• prefetching, by the prefetch circuit, one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, wherein the one or more further elements comprises a non-capability element and a capability element;
• or
• prefetching, by the prefetch circuit, one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object,
• determining, by the processor, if the respective element is a further capability comprising an address field of another respective element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a respective object to which the further capability authorizes access, and
• prefetching, by the prefetch circuit, the another respective element from the memory to the cache based on the respective element being the further capability.

A system comprising:

• a memory;
• a processor comprising:
• an execution circuit to execute an instruction that generates a memory access request for an element in memory via a first capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a first object to which the first capability authorizes access, and
• a cache separate from the memory;
• and
• a prefetch circuit to:
• prefetch an additional element from the memory to the cache,
• determine if the additional element is a second capability comprising an address field of a second element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a second object to which the second capability authorizes access, and
• prefetch the second element from the memory to the cache based on the additional element being the second capability
• wherein one of:
• the prefetch circuit is to determine that the additional element is a candidate pointer in a chain of linked pointers, and the prefetch of the additional element from the memory to the cache is based on the additional element being the candidate pointer;
• the prefetch circuit is to cause a prefetch of one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the prefetch circuit is to:
• determine if the one or more further elements is a respective capability comprising an address field of a respective element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a respective object to which the respective capability authorizes access, and
• prefetch the respective element from the memory to the cache for each of the one or more further elements that is the respective capability;
• the prefetch circuit is to cause a prefetch of one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the one or more further elements comprises a non-capability element and a capability element;
• or
• the prefetch circuit is to cause a prefetch of one or more further elements from the memory to the cache based on the second capability indicating the one or more further elements are within the second object, and the prefetch circuit is to:
• determine if the respective element is a further capability comprising an address field of another respective element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a respective object to which the further capability authorizes access, and
• prefetch the another respective element from the memory to the cache based on the respective element being the further capability.