Triple adder
AssigneeArm Limited
InventorsJavier Diaz Bruguera, David Raymond Lutz, Thomas Elmer, Nicholas Andrew Pfister
Life of this patent
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Abstract
A data processing apparatus is provided, which includes addition circuitry that performs a calculation of a sum of a first operand and a second operand. The addition circuitry produces an intermediate data prior to the calculation completing. Determination circuitry uses the intermediate data to produce the sum of the first operand and the second operand plus 1. Further determination circuitry configured to use the intermediate data to produce the sum of the first operand and the second operand plus 2.
Claims18
A data processing apparatus comprising:
- addition circuitry configured to perform a calculation of a sum of a first operand and a second operand, wherein the addition circuitry produces an intermediate data prior to the calculation completing;
- determination circuitry configured to use the intermediate data to produce the sum of the first operand and the second operand plus 1;
- and
- further determination circuitry configured to use the intermediate data to produce the sum of the first operand and the second operand plus 2
- the sum of the first operand and the second operand, the sum of the first operand and the second operand plus 1, and the sum of the first operand and the second operand plus 2 are produced using no more than one adder, for a same input.
A method of data processing comprising:
- performing a calculation of a sum of a first operand and a second operand, wherein the addition circuitry produces an intermediate data prior to the calculation completing;
- using the intermediate data to produce the sum of the first operand and the second operand plus 1;
- and
- using the intermediate data to produce the sum of the first operand and the second operand plus 2, wherein
- the sum of the first operand and the second operand, the sum of the first operand and the second operand plus 1, and the sum of the first operand and the second operand plus 2 are produced using no more than one adder, for a same input.
A non-transitory computer-readable medium to store computer-readable code for fabrication of a data processing apparatus comprising:
- addition circuitry configured to perform a calculation of a sum of a first operand and a second operand, wherein the addition circuitry produces an intermediate data prior to the calculation completing;
- determination circuitry configured to use the intermediate data to produce the sum of the first operand and the second operand plus 1;
- and
- further determination circuitry configured to use the intermediate data to produce the sum of the first operand and the second operand plus 2,
- the sum of the first operand and the second operand, the sum of the first operand and the second operand plus 1, and the sum of the first operand and the second operand plus 2 are produced using no more than one adder, for a same input.
Dependencies are inferred from the claim text.