Circuit, and waveform sensor
AssigneeRenesas Electronics Corporation
InventorsNorihito Katou, Fukashi Morishita
Life of this patent
Estimating the term…
Abstract
A circuit including a first circuit, a second circuit and a controller is provided, the first circuit and the second circuit each including a sample-and-hold circuit configured to hold a level of an input signal of a specific timing and an analog-to-digital converter circuit configured to convert the level of the input signal held in the sample-and-hold circuit into digital data and to output the digital data, the controller being configured to cause the first circuit to output the level of the input signal of a first timing and to cause the second circuit to output the level of the input signal of a second timing.
Claims6
A circuit comprising:
- a first circuit and a second circuit each comprising a sample-and-hold circuit configured to hold a level of an input signal of a specific timing and an analog-to-digital converter circuit configured to convert the level of the input signal held in the sample-and-hold circuit into digital data and to output the digital data, wherein the input signal is a sinusoidal signal detected by an antenna coil corresponding to a column of a waveform sensor;
- and
- a controller configured to cause the first circuit to output the level of the input signal of a first timing and to cause the second circuit to output the level of the input signal of a second timing.
A waveform sensor comprising:
- a first circuit and a second circuit each comprising an input section configured to receive an input signal changing along with elapse of time, a sample-and-hold circuit configured to hold a level of the input signal of a specific timing, and an analog-to-digital converter circuit configured to convert the level of the input signal held in the sample-and-hold circuit into digital data and to output the digital data, wherein the input signal is a sinusoidal signal detected by an antenna coil corresponding to a column of the waveform sensor;
- and
- a controller configured to cause the first circuit to output the level of the input signal of a first timing and to cause the second circuit to output the level of the input signal of a second timing.
Dependencies are inferred from the claim text.