# US 12,648,468 B2 · Wiring substrate

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- Number: US 12,648,468 B2
- Document ID: US12648468B2
- Status: Granted
- Kind: B2
- Application number: 18/403,954
- Filed: 2024-01-04
- Published: 2024-07-11
- Granted: 2026-06-02
- Earliest claimed: 2023-01-10
- Assignees: Shinko Electric Industries Co., Ltd.
- Applicants: Shinko Electric Industries Co., Ltd.
- Inventors: Toshiki Shirotori; Ryota Hoshina; Kenta Nakamura
- Web page: https://patentgrep.com/patent/US12648468B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H05K 1/0298: {Multilayer circuits}
- H05K 1/113: {Via provided in pad; Pad over filled via}
- H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H05K 2201/09563: Metal filled via
- H05K 2201/096: Vertically aligned vias, holes or stacked vias
- H05K 2201/09827: Tapered, e.g. tapered hole, via or groove
- H05K 2201/09845: Stepped hole, via, edge, bump or conductor
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A wiring substrate includes a first insulation layer, a first wiring layer including a pad formed on an upper surface of the first insulation layer, a second insulation layer formed on the upper surface of the first insulation layer to cover the first wiring layer, a first hole extending through the second insulation layer in a thickness-wise direction and partially exposing an upper surface of the pad, a second hole formed in the second insulation layer to be continuous with the first hole and widening a bottom opening of the first hole and entirely exposing a side surface of the pad in a thickness-wise direction, a via wiring filling the first hole and the second hole, and a second wiring layer formed on an upper surface of the second insulation layer integrally with the via wiring. The second hole partially exposes the upper surface of the first insulation layer.

## Claims

### Claim 1

A wiring substrate, comprising:
a first insulation layer;
a first wiring layer including a pad formed on an upper surface of the first insulation layer;
a second insulation layer formed on the upper surface of the first insulation layer to cover the first wiring layer;
a first hole extending through the second insulation layer in a thickness-wise direction of the second insulation layer and exposing a portion of an upper surface of the pad, the first hole including a first wall extending downward from an upper surface of the second insulation layer;
a second hole formed in the second insulation layer to be continuous with the first hole, the second hole increasing a width of a bottom opening of the first hole thereby exposing a portion of the upper surface of the first insulation layer and entirely exposing a side surface of the pad in a thickness-wise direction of the pad, the second hole including:
a second wall extending from a lower end of the first wall to an outer side of the first hole;
a third wall extending from an outer end of the second wall to the upper surface of the first insulation layer; and
a first gap defined between the side surface of the pad and the third wall, the first gap narrowing between the side surface of the pad and the third wall from the upper surface of the pad toward a lower surface of the pad;
a via wiring filling the first hole and the second hole; and
a second wiring layer formed on the upper surface of the second insulation layer integrally with the via wiring.

### Claim 2 (depends on 1)

The wiring substrate according to claim 1, wherein the third wall extends perpendicular to the upper surface of the first insulation layer, and the side surface of the pad is inclined toward the third wall from the upper surface of the pad toward the lower surface of the pad.

### Claim 3 (depends on 1)

The wiring substrate according to claim 1, wherein the via wiring includes a tapered via conductor filling the first hole, and a tubular via conductor filling the second hole and formed integrally with the tapered via conductor, and the tubular via conductor entirely covers the upper surface of the pad and the side surface of the pad.

### Claim 4 (depends on 1)

The wiring substrate according to claim 1, wherein the second wall extends in a planar direction that is orthogonal to the thickness-wise direction of the second insulation layer.

### Claim 5 (depends on 1)

The wiring substrate according to claim 1, wherein the second wall is inclined downward from the lower end of the first wall to an upper end of the third wall.

### Claim 6 (depends on 1)

The wiring substrate according to claim 1, wherein the first wall is inclined toward a center of the first hole in plan view from the upper surface of the second insulation layer toward the upper surface of the pad.

### Claim 7 (depends on 1)

The wiring substrate according to claim 1, wherein the second hole is formed around the pad along an entire perimeter of the pad, and the via wiring entirely covers the side surface of the pad.

### Claim 8 (depends on 1)

The wiring substrate according to claim 1, wherein the via wiring includes a seed layer covering the first wall, the second wall, the third wall, the upper surface of the first insulation layer exposed from the second hole, the side surface of the pad, and the upper surface of the pad, and a metal layer formed on the seed layer and filling the first hole and the second hole.