Semiconductor device and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChing-Jung Yang, Hsien-Wei Chen, Ming-Fa Chen
Life of this patent
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Abstract
A semiconductor device includes a metallic pattern provided above a substrate and extending in a first direction with a first width, a first active metallic feature directly connected to the metallic pattern and extending in a second direction from the metallic pattern with a second width that is smaller than the first width, and a first dummy metallic feature arranged adjacently to the first active metallic feature. The first dummy metallic feature is directly connected to the metallic pattern and extends in the second direction from the metallic pattern while not electrically connected to lines other than the metallic pattern.
Claims20
A semiconductor structure, comprising:
- an interconnect structure underlying a substrate and including a first metallic pattern extending in a first direction with a first width and a second metallic pattern above the first metallic pattern;
- a first active metallic feature connected to the first metallic pattern and extending in a second direction from the first metallic pattern with a second width that is smaller than the first width;
- a first dummy metallic feature arranged adjacently to the first active metallic feature, directly connected to the first metallic pattern, and extending in the second direction from the first metallic pattern while not electrically connected to lines other than the first metallic pattern;
- a through substrate via penetrating through the substrate and landing on the second metallic pattern, and a bottom surface of the through substrate via is lower than a bottom surface of the substrate;
- a second active metallic feature underlying the first active metallic feature and extending in the second direction;
- a first dielectric layer laterally covering the first active metallic feature;
- a second dielectric layer laterally covering the second active metallic feature, the second dielectric layer being directly bonded to the first dielectric layer, and the second active metallic feature being directly bonded to the first active metallic feature at a bonding interface between the second dielectric layer and the first dielectric layer;
- and
- a second dummy metallic feature extending in the second direction, the second dummy metallic feature being directly bonded to the first dummy metallic feature, wherein the second dummy metallic feature is electrically floating, wherein the first dielectric layer laterally covers the first dummy metallic feature, the second dielectric layer laterally covers the second dummy metallic feature, and at the bonding interface between the second dielectric layer and the first dielectric layer, the second active metallic feature and the first active metallic feature have the same width.
A semiconductor structure, comprising:
- an interconnect structure underlying a first substrate and including a first metallic pattern extending in a first direction with a first width;
- a plurality of first active metallic features connected to the first metallic pattern and extending in a second direction from the first metallic pattern with a second width that is smaller than the first width;
- a first dummy metallic feature arranged adjacently to one side of an array of the first active metallic features, directly connected to the first metallic pattern, and extending in the second direction from the first metallic pattern while not electrically connected to lines other than the first metallic pattern;
- a through substrate via penetrating through the first substrate and extending into the interconnect structure to be electrically coupled to the first active metallic features, and a bottom surface of the through substrate via is lower than a bottom surface of the substrate;
- a plurality of second active metallic features underlying the first active metallic feature and extending in the second direction, wherein the second active metallic features and the first active metallic features are tapered in opposing directions;
- a second metallic pattern provided above a second substrate and extending in the first direction, wherein each of the second active metallic features comprises one end connected to an active portion of the second metallic pattern and an opposing end directly connected to a corresponding one of the first active metallic features;
- and
- a second dummy metallic feature arranged adjacently to one side of an array of the second active metallic features, the second dummy metallic feature comprising one end directly connected to a dummy portion of the second metallic pattern and an opposing end directly connected to the second dummy metallic feature.
Dependencies are inferred from the claim text.