Forming 3D transistors using 2D van der WAALS materials
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSheng-Kai Su, Jin Cai
Life of this patent
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Abstract
A method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. Horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.
Claims20
A method comprising:
- etching a dielectric layer to form a dielectric fin;
- depositing a transition metal dichalcogenide layer on the dielectric fin;
- performing a first anisotropic etching process on the transition metal dichalcogenide layer, wherein horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring;
- forming a gate stack on a first portion of the vertical semiconductor ring;
- and
- forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of the vertical semiconductor ring.
A method of manufacturing a semiconductor device, the method comprising:
- forming a dielectric fin;
- forming a 2D material layer on sidewalls of the dielectric fin, wherein a top surface of the dielectric fin is exposed after forming the 2D material layer;
- forming a gate stack on the dielectric fin and the 2D material layer, wherein the gate stack contacts a first portion of a sidewall of the 2D material layer, and wherein the gate stack contacts the top surface of the dielectric fin;
- and
- forming a source/drain contact plug contacting a second portion of the sidewall of the 2D material layer, wherein the source/drain contact plug is free of the 2D material.
A method of manufacturing a semiconductor device, the method comprising:
- forming a dielectric fin on a dielectric layer;
- forming a semiconductor ring on sidewalls of the dielectric fin, the semiconductor ring comprising a transition metal dichalcogenide material;
- forming a gate stack on a top surface of the dielectric fin and a first portion of a top surface of the semiconductor ring;
- and
- forming a source/drain contact plug on a second portion of the top surface of the semiconductor ring, wherein the source/drain contact plug overlaps the top surface of the dielectric fin in a top-down view.
Dependencies are inferred from the claim text.