Multi-gate device fabrication methods and related structures

A method, comprising:

• providing a first fin in an N-type device region and a second fin in a P-type device region, wherein each of the first and second fins include a plurality of semiconductor channel layers;
• forming a gate dielectric surrounding each of the plurality of semiconductor channel layers within each of the N-type device region and the P-type device region;
• depositing a first metal film surrounding the gate dielectric in the P-type device region, wherein the first metal film includes at least Al;
• performing a first annealing process to modulate a first flatband voltage (Vfb) of the gate dielectric in the P-type device region;
• and
• removing the first metal film.

A method, comprising:

• providing a P-type device in a P-type device region and an N-type device in an N-type device region, wherein each of the P-type device and the N-type device include a plurality of channel layers, and wherein the P-type device and the N-type device are electrically isolated from each other by a dielectric wall formed therebetween;
• forming a dielectric layer on three sides of each of the plurality of channel layers of the P-type device and the N-type device;
• depositing a metal film stack over the dielectric layer of the P-type device;
• after performing an annealing process to modulate a flatband voltage (Vfb) of the P-type device, removing the metal film stack;
• and
• after removing the metal film stack, forming an additional dielectric layer over the dielectric layer on the three sides of each of the plurality of channel layers of the P-type device and the N-type device.