Semiconductor devices

A semiconductor device comprising:

• a plurality of channels spaced apart from each other on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate;
• a gate structure on the substrate and covering upper and lower surfaces and a sidewall of a portion of each channel of the plurality of channels;
• a gate spacer on a sidewall of a first portion of the gate structure, the first portion of the gate structure being disposed on an uppermost channel of the plurality of channels;
• a source/drain layer on a portion of the substrate adjacent to the gate structure and contacting sidewalls of the plurality of channels;
• a first contact plug on the source/drain layer and contacting an outer wall of the gate spacer,
• wherein the first portion of the gate structure includes:
• a first conductive pattern having:
• a lower portion on the uppermost channel of the plurality of channels;
• and
• an upper portion on the lower portion with a width greater than a width of the lower portion and contacting an inner sidewall of the gate spacer;
• a second conductive pattern on a lower surface and a sidewall of the lower portion of the first conductive pattern;
• and
• a gate insulating pattern on a lower surface and an outer sidewall of the second conductive pattern and contacting an upper surface of the uppermost channel of the plurality of channels and the inner sidewall of the gate spacer, and
• wherein an upper surface of the first conductive pattern is substantially coplanar with an upper surface of the first contact plug-;
• and
• a second contact plug contacting the upper surface of the first conductive pattern, wherein a lower surface of the second contact plug has a first width, and wherein the upper surface of the first conductive pattern has a second width greater than the first width.

A semiconductor device comprising:

• an active pattern on a substrate;
• a gate structure on the active pattern,
• wherein the gate structure includes:
• a first conductive pattern having:
• a lower portion;
• and
• an upper portion on the lower portion with a width greater than that of the lower portion;
• a second conductive pattern on a lower surface and a sidewall of the lower portion of the first conductive pattern;
• and
• a gate insulating pattern on a lower surface and an outer sidewall of the second conductive pattern;
• a gate spacer on a sidewall of the gate structure;
• a source/drain layer on a portion of the active pattern adjacent to the gate structure;
• a first contact plug on the source/drain layer and contacting an outer sidewall of the gate spacer;
• a second contact plug contacting an upper surface of the first conductive pattern, wherein a lower surface of the second contact plug has a first width, and wherein the upper surface of the first conductive pattern has a second width greater than the first width;
• and
• a via contacting an upper surface of the first contact plug,
• wherein the upper portion of the gate structure contacts an inner sidewall of the gate spacer, and
• wherein the upper surface of the first conductive pattern is substantially coplanar with the upper surface of the first contact plug.