Transistor gate isolation structures and methods of forming the same

A method comprising:

• etching an opening between a first gate structure and a second gate structure;
• forming a gate isolation structure between the first gate structure and the second gate structure by:
• depositing an isolation layer in the opening between the first gate structure and the second gate structure, wherein depositing the isolation layer forms a seam in the gate isolation structure, the seam comprising a portion of the opening unfilled by the isolation layer;
• and
• shrinking the seam in the isolation layer by expanding the isolation layer, wherein expanding the isolation layer comprises increasing a concentration of an element in a material of the isolation layer;
• forming an inter-layer dielectric over the gate isolation structure, the first gate structure, and the second gate structure;
• and
• forming a first contact and a second contact through the inter-layer dielectric, the gate isolation structure disposed between the first contact and the second contact.

A method comprising:

• dividing a first gate structure into a plurality of second gate structures by etching an opening through the first gate structure, the opening physically separating the first gate structure into the second gate structures;
• forming a gate isolation structure between the second gate structures by:
• depositing an isolation layer in the opening, the isolation layer comprising an expandable dielectric material;
• and
• expanding the isolation layer in the opening by bombarding the isolation layer with ions of an element that induces cross-linking of the expandable dielectric material;
• and
• forming an inter-layer dielectric over the gate isolation structure and the second gate structures.