Thin film transistor array substrate, display panel and display device

A thin film transistor array substrate comprising a semiconductor layer, a gate layer and a source-drain layer arranged in a stacked manner, two insulating layers respectively located between the semiconductor layer and the gate layer and between the gate layer and the source-drain layer, wherein

• the semiconductor layer comprises a source region, a drain region and a channel region located between the source region and the drain region, the channel region is doped with a p-type impurity having a molecular weight equal to or greater than 25, a range of a doping depth of the p-type impurity in the channel region is 5 nm to 10 nm, a surface layer of the channel region close to the gate layer is doped with the p-type impurity, and a range of a doping concentration per the doping depth of the p-type impurity in the channel region is 3×1011 cm−2 to 2×1012 cm−2,
• the gate layer comprises a gate arranged corresponding to the channel region,
• the source-drain layer comprises a source and a drain separated from each other, the source is electrically connected to the source region, and the drain is electrically connected to the drain region,
• the source region and the drain region have undergone two ion implantation processes, and the channel region has undergone one ion implantation processes,
• a range of a doping concentration of the p-type impurity in the source region and the drain region is 5×1014 cm−2 to 2×1015 cm−2.