Multiple gate patterning methods towards future nanosheet scaling

A method for forming a semiconductor device, comprising:

• forming first channel nanostructures in an n-type device region and second channel nanostructures in a p-type device region;
• forming an interfacial layer to surround each of the first channel nanostructures and each of the second channel nanostructures, wherein the interfacial layer has a thickness ranging from about 1.25 nm to about 1.5 nm;
• depositing a gate dielectric layer on the interfacial layer to surround each of the first channel nanostructures and each of the second channel nanostructures;
• depositing a sacrificial layer on the gate dielectric layer to surround each of the first channel nanostructures and each of the second channel nanostructures, wherein the sacrificial layer merges in first spaces between the first channel nanostructures and merges in second spaces between the second channel nanostructures, wherein the sacrificial layer comprises a dielectric material;
• etching the sacrificial layer such that only portions of the sacrificial layer disposed in the first spaces between the first channel nanostructures and disposed in the second spaces between the second channel nanostructures remain;
• removing the sacrificial layer from the n-type device region;
• depositing an n-type work function metal layer on the gate dielectric layer to surround each of the first channel nanostructures in the n-type device region and on the gate dielectric layer and the sacrificial layer in the p-type device region;
• depositing a cap layer on the n-type work function metal layer in both the n-type device region and the p-type device region, wherein the cap layer surrounds each of the first channel nanostructures and merges in the first spaces between the first channel nanostructures;
• removing the n-type work function metal layer and the cap layer from the p-type device region;
• and
• depositing a p-type work function metal layer to surround each of the second channel nanostructures in the p-type device region and to cover the cap layer in the n-type device region, wherein the p-type work function metal layer merges in the second spaces between the second channel nanostructures.

A method for forming a semiconductor device, comprising:

• providing, for an n-type transistor, vertically stacked first channel nanostructures spaced apart by first spaces, and, for a p-type transistor, vertically stacked second channel nanostructures spaced apart by second spaces;
• depositing a gate dielectric layer around the first and second channel nanostructures;
• forming an n-type metal gate layer on the gate dielectric layer and around the first and second channel nanostructures, the n-type metal gate layer filling the first spaces and the second spaces;
• forming a patterned mask layer to cover a portion of the n-type metal gate layer over the first channel nanostructures, while exposing a portion of the n-type metal gate layer over the second channel nanostructures;
• removing the exposed portion of the n-type metal gate layer from the second channel nanostructure to re-expose the second spaces;
• removing the patterned mask layer;
• and
• depositing a p-type work function metal layer on a portion of the gate dielectric layer around the second channel nanostructures and on a remaining portion of the n-type metal gate layer around the first channel nanostructures, the p-type work function metal layer filling the second spaces.