Fabrication of gate-all-around integrated circuit structures having additive gate structures

An integrated circuit structure, comprising:

• a first vertical arrangement of horizontal nanowires;
• a second vertical arrangement of horizontal nanowires;
• a first P-type gate stack over the first vertical arrangement of horizontal nanowires, the first P-type gate stack having a first P-type conductive layer over a first gate dielectric, and the intervening conductive seed layer between the first P-type conductive layer and the first gate dielectric;
• and
• a second P-type gate stack over the second vertical arrangement of horizontal nanowires, the second P-type gate stack having a second P-type conductive layer over a second gate dielectric, and the intervening conductive seed layer between the second P-type conductive layer and the second gate dielectric, wherein the second P-type gate stack is different than the first P-type gate stack, wherein the first P-type gate stack is in contact with the second P-type gate stack, and wherein the intervening conductive seed layer comprises molybdenum and silicon, or the intervening conductive seed layer comprises tungsten and silicon.

An integrated circuit structure, comprising:

• a first vertical arrangement of horizontal nanowires;
• a second vertical arrangement of horizontal nanowires;
• a first N-type gate stack over the first vertical arrangement of horizontal nanowires, the first N-type gate stack having a first N-type conductive layer over a first gate dielectric, and an intervening conductive seed layer between the first N-type conductive layer and the first gate dielectric;
• and
• a second N-type gate stack over the second vertical arrangement of horizontal nanowires, the second N-type gate stack having a second N-type conductive layer over a second gate dielectric, and the intervening conductive seed layer between the second N-type conductive layer and the second gate dielectric, wherein the second N-type gate stack is different than the first N-type gate stack, wherein the first N-type gate stack is in contact with the second N-type gate stack, and wherein the intervening conductive seed layer comprises molybdenum and silicon, or the intervening conductive seed layer comprises tungsten and silicon.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first vertical arrangement of horizontal nanowires;
• a second vertical arrangement of horizontal nanowires;
• a P-type gate stack over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric, and an intervening conductive seed layer between the P-type conductive layer and the first gate dielectric;
• and
• an N-type gate stack over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric, and the intervening conductive seed layer between the N-type conductive layer and the second gate dielectric, wherein the P-type gate stack is in contact with the N-type gate stack, and wherein the intervening conductive seed layer comprises molybdenum and silicon, or the intervening conductive seed layer comprises tungsten and silicon.