US 12,648,153 B2Granted

Semiconductor device packages and methods of formation

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChih-Wei Wu, Ying-Ching Shih, Wen-Chih Chiou, An-Jhih Su, Chia-Nan Yuan

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Abstract

A system on chip (SoC) die package is attached to a redistribution structure of a semiconductor device package such that a top surface of the SoC die package is above a top surface of an adjacent memory die package. This may be achieved through the use of various attachment structures that increase the height of the SoC die package. After encapsulating the memory die package and the SoC die package in an encapsulation layer, the encapsulation layer is grinded down. The top surface of the SoC die package being above the top surface of the adjacent memory die package results in the top surface of the SoC die package being exposed through the encapsulation layer after the grinding operation. This enables heat to be dissipated through the top surface of the SoC die package.

Claims20

Dependent claims

A semiconductor device package, comprising:

a redistribution structure, comprising:
one or more dielectric layers;
and
a plurality of metallization layers, included in the one or more dielectric layers;
a plurality of connection terminals attached to a first side of the redistribution structure;
a first semiconductor die package attached to a second side of the redistribution structure opposing the first side;
a plurality of conductive extension structures attached to the second side of the redistribution structure;
and
a second semiconductor die package attached to the plurality of conductive extension structures,
wherein the first semiconductor die package and the second semiconductor die package are side by side in the semiconductor device package, and
wherein a height of a top surface of the second semiconductor die package, relative to a top surface of the redistribution structure, is greater relative to a height of a top surface of the first semiconductor die package in the semiconductor device package relative to the top surface of the redistribution structure.

8 more elements

A semiconductor device package, comprising:

a redistribution structure, comprising:
one or more dielectric layers;
and
a plurality of metallization layers, included in the one or more dielectric layers;
a plurality of connection terminals attached to a first side of the redistribution structure;
a first semiconductor die package attached to a second side of the redistribution structure opposing the first side;
and
a second semiconductor die package side by side with the first semiconductor die package and attached to the second side of the redistribution structure, comprising:
a semiconductor die;
a plurality of conductive structures under the semiconductor die and coupled with the redistribution structure;
a first polymer layer under the semiconductor die;
and
a second polymer layer under the first polymer layer,
wherein the plurality of conductive structures extend through the first polymer layer and the second polymer layer, and
wherein a top surface of the second semiconductor package is higher than a top surface of the first semiconductor package based on the plurality of conductive structures.

12 more elements

A semiconductor device package, comprising:

a redistribution structure, comprising:
one or more dielectric layers;
and
a plurality of metallization layers, included in the one or more dielectric layers;
a plurality of connection terminals attached to a first side of the redistribution structure;
a first semiconductor die package attached to a second side of the redistribution structure opposing the first side;
an adaptor structure attached to the second side of the redistribution structure;
and
a second semiconductor die package attached to the adaptor structure,
wherein the first semiconductor die package and the second semiconductor die package are side by side in the semiconductor device package, and
wherein a top surface of the second semiconductor die package is above a top surface of the first semiconductor die package in the semiconductor device package.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/150,569Filed 5 Jan 2023 · us provisional application
Priority: 27 Sep 2022
Published: US 2024/0107780 A128 Mar 2024
Granted: 2 Jun 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification29 codes

H10B 80/00
Assemblies of multiple devices comprising at least one memory device covered by
H10W 74/019
Manufacture or treatment: using temporary auxiliary substrates
H10P 72/74
For supporting or gripping: using temporarily an auxiliary support
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]