Semiconductor device and electronic device

A semiconductor device comprising:

• a memory cell and a circuit,
• wherein the memory cell comprises a first transistor, a first FTJ element, and a second FTJ element,
• wherein the first FTJ element and the second FTJ element each comprise an input terminal, a tunnel insulating film, a dielectric, and an output terminal,
• wherein the input terminal, the tunnel insulating film, the dielectric, and the output terminal overlap with each other in this order in each of the first FTJ element and the second FTJ element,
• wherein the circuit comprises a switch, an operational amplifier, and a load,
• wherein one of a source and a drain of the first transistor is directly connected to the output terminal of the first FTJ element and the input terminal of the second FTJ element,
• wherein the other of the source and the drain of the first transistor is electrically connected to a first terminal of the switch,
• wherein a second terminal of the switch is electrically connected to an inverting input terminal of the operational amplifier and a first terminal of the load,
• wherein an output terminal of the operational amplifier is electrically connected to a second terminal of the load,
• wherein the load comprises at least one of a resistor, a capacitor, and a transistor, and
• wherein data of the memory cell is read from a difference in an amount of currents flowing between the input terminals and the output terminals of the first FTJ element and the second FTJ element.

A semiconductor device comprising:

• a memory cell and a circuit,
• wherein the memory cell comprises a first transistor, a first circuit element, and a second circuit element,
• wherein the circuit comprises a switch, an operational amplifier, and a load,
• wherein one of a source and a drain of the first transistor is directly connected to an output terminal of the first circuit element and an input terminal of the second circuit element,
• wherein the other of the source and the drain of the first transistor is electrically connected to a first terminal of the switch,
• wherein a second terminal of the switch is electrically connected to an inverting input terminal of the operational amplifier and a first terminal of the load,
• wherein an output terminal of the operational amplifier is electrically connected to a second terminal of the load,
• wherein the first circuit element and the second circuit element each comprise any one of a variable resistor, an MTJ element, and a phase change memory element,
• wherein the load comprises at least one of a resistor, a capacitor, and a transistor, and
• wherein data of the memory cell is read from a difference in an amount of currents flowing between the input terminals and the output terminals of the first circuit element and the second circuit element.