3D semiconductor device and structure with logic and memory

A 3D semiconductor device, the device comprising:

• a first level comprising a first single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors,
• wherein said first level comprises a first metal layer, a second metal layer, and a third metal layer, and
• wherein connection of said plurality of first transistors comprises said first metal layer, and/or said second metal layer, and/or said third metal layer;
• a plurality of second transistors disposed atop said first level;
• a plurality of third transistors disposed atop said plurality of second transistors;
• a fourth metal layer disposed atop said plurality of third transistors;
• a memory array comprising word-lines,
• wherein said memory array comprises at least four memory mini-arrays,
• wherein each of said memory mini-arrays comprises at least four rows by four columns of memory cells,
• wherein at least one of said plurality of second transistors comprises a metal gate, and
• wherein each of said memory cells comprises at least one of said plurality of second transistors or at least one of said plurality of third transistors;
• and
• a connection path from said fourth metal to said third metal,
• wherein said connection path comprises a via disposed through said memory array, and
• wherein said memory control circuit comprises at least one SRAM cache memory circuit.

A 3D semiconductor device, the device comprising:

• a first level comprising a first single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors,
• wherein said first level comprises a first metal layer, a second metal layer, and third metal layer, and
• wherein connection of said plurality of first transistors comprises said first metal layer, and/or said second metal layer, and/or said third metal layer;
• a plurality of second transistors disposed atop said first level;
• a plurality of third transistors disposed atop said plurality of second transistors;
• a fourth metal layer disposed atop said plurality of third transistors;
• a memory array comprising word-lines,
• wherein said memory array comprises at least four memory mini-arrays,
• wherein each of said memory mini-arrays comprises at least four rows by four columns of memory cells,
• wherein at least one of said plurality of second transistors comprises a metal gate, and
• wherein each of said memory cells comprises at least one of said plurality of second transistors or at least one of said plurality of third transistors;
• and
• a connection path from said fourth metal to said third metal,
• wherein said connection path comprises a via disposed through said memory array, and
• wherein said memory control circuit comprises a plurality of antifuse elements.