Power supplying circuit and associated switch controller for non-volatile memory
AssigneeeMemory Technology Inc.
InventorWei-Chiang Ong
Life of this patent
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Abstract
A power supplying circuit and an associated switch controller for a non-volatile memory are provided. When the sector erase is performed, the voltage stress withstood by the switching transistors in the power supplying circuit is lower than the maximum voltage stress. In addition, the voltage stress withstood by all transistors in the switch controller is lower than the maximum voltage stress. In other words, when the sector erase is performed, all switch controllers and all switching transistors in the power supplying circuit can be operated normally. In addition, an erase voltage is provided to a specified sector of the array structure, so that all memory cells in the specified sector are erased into the erase state.
Claims22
A power supplying circuit for a non-volatile memory, the power supplying circuit comprising a voltage source and a switching circuit, the voltage source outputting a high voltage, a low voltage and a decoupling signal, the switching circuit comprising a power switch and a switch controller, a first terminal of the power switch receiving the high voltage, a second terminal of the power switch being coupled to an erase line of the non-volatile memory, the switch controller comprising:
- a latch, wherein a first power terminal of the latch receives the high voltage, a second power terminal of the latch receives the low voltage, a first control terminal of the latch is connected with a first node, and a second control terminal of the latch is connected with a second node;
- a first driving stage, wherein a first power terminal of the first driving stage receives the high voltage, a second power terminal of the first driving stage receives the low voltage, an input terminal of the first driving stage is connected with the first node, an output terminal of the first driving stage generates a switching signal to a control terminal of the power switch, and on/off states of the power switch are controlled according to the switching signal;
- a first control stage connected with the first node, wherein the first control stage receives a control signal and the decoupling signal;
- and
- a second control stage connected with the second node, wherein the second control stage receives an inverted control signal and the decoupling signal,
- wherein in a logic phase of a sector erase, the high voltage is equal to a logic supply voltage, the low voltage is equal to a ground voltage, and the control signal is stored in the latch;
- wherein in a transition phase of the sector erase, the high voltage rises from the logic supply voltage to a first voltage, the low voltage is equal to the ground voltage;
- wherein in an erase phase of the sector erase, the high voltage rises from the first voltage to an erase voltage, the low voltage rises from the ground voltage to a second voltage, the erase voltage is higher than the second voltage, and the first driving stage generates the switching signal according to the high voltage and the low voltage;
- wherein the decoupling signal is in a range of the high voltage and the low voltage during the logic phase, the transition phase and the erase phase.
A power supplying circuit for a non-volatile memory, wherein the power supplying circuit comprises a power switch, a switch controller and a voltage source, the voltage source is configured to output a high voltage, a low voltage and a decoupling signal, a first terminal of the power switch is configured to receive the high voltage, a second terminal of the power switch is coupled to an erase line of the non-volatile memory, the switch controller is configured to receive the high voltage, the low voltage and the decoupling signal and the switch controller comprises:
- a latch, wherein a first control terminal of the latch is coupled to a first node, and a second control terminal of the latch is coupled to a second node;
- a first driving stage coupled to the first node and a control terminal of the power switch, and configured to output the high voltage or the low voltage as a switching signal to the control terminal of the power switch according to a voltage at the first node;
- a first control stage coupled to the first node, and configured to control the voltage at the first node according to a control signal and the decoupling signal;
- and
- a second control stage coupled to the second node, and configured to control a voltage at the second node according to an inverted control signal and the decoupling signal,
- wherein the high voltage, the low voltage and the decoupling signal are increased in a multi-step manner during a sector erase of the non-volatile memory, wherein the decoupling signal is in a range of the high voltage and the low voltage during the sector erase.
Dependencies are inferred from the claim text.