Non-volatile memory device having a plurality of pass transistors

A non-volatile memory device comprising:

• a memory cell array including a plurality of memory blocks;
• and
• a row decoder block connected to the plurality of memory blocks via a ground selection line, a word line and a string selection line, wherein
• the row decoder block includes
• a semiconductor substrate,
• a first pass transistor on a first region of the semiconductor substrate and connected to the ground selection line,
• a second pass transistor on a second region of the semiconductor substrate and connected to the word line, and
• a third pass transistor on a third region of the semiconductor substrate and connected to the string selection line,
• each of the first region, the second region, and the third region is a region doped to a depth from a top surface of the semiconductor substrate,
• the first region, the second region, and the third region are insulated from one another by an implant region at the semiconductor substrate,
• the implant region includes a side wall region surrounding a side wall of each of the first region, the second region and the third region, and a deep well region surrounding a bottom surface of each of the first region, the second region and the third region,
• the first region includes a first doped region and a first well region doped beneath the first doped region, the first well region having a higher concentration than the first doped region,
• the second region includes a second doped region and a second well region doped beneath the second doped region, the second well region having a higher concentration than the second doped region,
• a first contact extends through the first doped region and contacts the first well region, wherein the first contact is surrounded by and laterally contacts the first doped region, and a second contact extends through the second doped region and contacts the second well region, wherein the second contact is surrounded by and laterally contacts the second doped region, and
• the first well region is configured to receive a first voltage via the first contact while a first input voltage is being applied to the first pass transistor, the second well region is configured to receive a second voltage via the second contact while a second input voltage is being applied to the second pass transistor, and a level of the first voltage and a level of the second voltage are different from a ground voltage level.

A non-volatile memory device comprising:

• a memory cell array including a plurality of memory blocks;
• and
• a row decoder block connected to the plurality of memory blocks via a ground selection line, a word line, a dummy word line and a string selection line, wherein
• the row decoder block includes
• a semiconductor substrate,
• a first pass transistor on a first region of the semiconductor substrate and connected to the ground selection line,
• a second pass transistor on a second region of the semiconductor substrate and connected to the word line or the dummy word line, and
• a third pass transistor on a third region of the semiconductor substrate and connected to the string selection line,
• each of the first region, the second region, and the third region is a region doped to a depth from a top surface of the semiconductor substrate,
• the semiconductor substrate includes a side wall region surrounding a side wall of each of the first region, the second region and the third region, and a deep well region surrounding a bottom surface of each of the first region, the second region and the third region,
• an implant region is a region doped in a concentration, and insulates the first region, the second region and the third region from one another,
• the first region includes a first doped region and a first well region doped beneath the first doped region, the first well region having a higher concentration than the first doped region,
• the second region includes a second doped region and a second well region doped beneath the second doped region, the second well region having a higher concentration than the second doped region,
• a first voltage signal having a lower level than a first input voltage signal of the first pass transistor is configured to be applied to the first well region via a first contact extending through the first doped region, wherein the first contact is surrounded by and laterally contacts the first doped region, and
• a second voltage signal having a lower level than a second input voltage signal of the second pass transistor is configured to be applied to the second well region via a second contact extending through the second doped region, wherein the second contact is surrounded by and laterally contacts the second doped region.