Demodulator circuit
AssigneeInfineon Technologies AG
InventorMarco Bucci
Life of this patent
Estimating the term…
Abstract
A demodulator includes a sampling stage, a hold stage, and an output stage. The sampling stage includes at least one mixer configured to be controlled by complementary clock signals synchronous with a carrier frequency of an input signal to demodulate the input signal and generate a sampled signal. The hold stage includes at least a first capacitor circuit configured to output the sampled signal after delaying the sampled signal as a first hold signal and a second capacitor circuit configured to output the sampled signal after delaying the sampled signal as a second hold signal. The output stage is configured to alternately couple the first hold signal and the second hold signal as a demodulated output signal.
Claims20
A demodulator, comprising:
- a sampling stage comprising at least one mixer configured to be controlled by complementary clock signals synchronous with a carrier frequency of an input signal to demodulate the input signal and generate a sampled signal;
- a hold stage comprising at least a first capacitor circuit configured to output the sampled signal after delaying the sampled signal as a first hold signal and a second capacitor circuit configured to output the sampled signal after delaying the sampled signal as a second hold signal;
- and
- an output stage configured to alternately couple the first hold signal and the second hold signal as a demodulated output signal.
A method, comprising:
- controlling at least one mixer with complementary clock signals synchronous with a carrier frequency of an input signal to demodulate the input signal and generate a sampled signal;
- delaying, by a first capacitor circuit, the sampled signal to output a first hold signal;
- delaying, by a second capacitor circuit, the sampled signal to output a second hold signal;
- and
- alternately coupling the first hold signal and the second hold signal as a demodulated output signal.
A near field communication (NFC) receiver, comprising:
- a demodulator that includes:
- at least one mixer configured to be controlled by complementary clock signals synchronous with a carrier frequency of an input signal to demodulate the input signal and generate a sampled signal;
- at least a first capacitor circuit configured to output the sampled signal after delaying the sampled signal as a first hold signal and a second capacitor circuit configured to output the sampled signal after delaying the sampled signal as a second hold signal;
- and
- at least one switch configured to alternately couple the first hold signal and the second hold signal as a demodulated output signal.
Dependencies are inferred from the claim text.