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AssigneeCadence Design Systems, Inc.
InventorsHajee Mohammed Shuaeb Fazeel, Vinod Kumar, Thomas Evan Wilson
Estimating the term…
Embodiments included herein are directed towards a sampler circuit. Embodiments may include a first positive-channel metal oxide semiconductor (PMOS) or negative-channel metal oxide semiconductor (NMOS) transistor that may be operatively connected to a voltage source and a first output node. A cross-coupled PMOS/NMOS pair may be operatively connected to the first PMOS/NMOS transistor, respectively, and a pair of first stage output nodes may be operatively connected to the cross-coupled PMOS/NMOS pair, respectively, where the pair of first stage output nodes may include a positive node and a negative node. An input differential pair may be operatively connected to the pair of first stage output nodes, and an offset current digital-to-analog converter (DAC) may be operatively connected to a first side of the input differential pair, while an offset current DAC replica may be operatively connected to a second side of the input differential pair.
A sampler circuit comprising:
A sampler circuit comprising:
A sampler circuit comprising:
Dependencies are inferred from the claim text.