Hybrid and adaptive offset calibration for SAR ADC
AssigneeQUALCOMM Incorporated
InventorsYongjian Tang, Kenneth Luis Arcudia
Life of this patent
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Abstract
A SAR ADC is provided with a hybrid offset calibration that includes a digital calibration without bit extension. Due to the lack of bit extension, the digital calibration can only address integer multiples of least-significant bits for the offset. The hybrid offset calibration further includes an analog calibration that addresses a remaining fraction of a least-significant bit of the offset.
Claims20
A successive-approximation-register (SAR) analog-to-digital converter (ADC) system, comprising:
- a SAR ADC configured to convert an analog input signal into an uncorrected digital output signal, the SAR ADC including an analog calibration circuit responsive to an analog calibration code;
- a digital adder configured to add a digital calibration code to the uncorrected digital output signal to produce a corrected digital output signal;
- and
- a controller configured to adjust the digital calibration code and the analog calibration code responsive to a DC offset in the uncorrected digital output signal.
A method of calibrating a DC offset of an uncorrected digital output signal of a SAR ADC, comprising:
- adding a digital calibration code to the uncorrected digital output signal responsive to the DC offset of the uncorrected digital output signal to form a corrected digital output signal, wherein the digital calibration code equals an integer multiple of a least-significant bit (LSB) of the DC offset;
- and
- adjusting an analog calibration circuit in the SAR ADC to substantially eliminate a remaining fraction of the LSB of the DC offset.
A serializer-deserializer receiver, comprising:
- a continuous-time linear equalizer configured to process an input signal to produce a plurality of analog-to-digital converter (ADC) input signals;
- a plurality of ADC slices corresponding to the plurality of ADC input signals, each ADC slice including a successive-approximation register (SAR) ADC system configured to digitize a corresponding one of the ADC input signals, wherein each SAR ADC system comprises:
- a SAR ADC configured to convert an analog input signal into an uncorrected digital output signal having a DC offset, the SAR ADC including an analog calibration circuit responsive to an analog calibration code;
- a digital adder configured to add a digital calibration code to the uncorrected digital output signal to produce a corrected digital output signal;
- and
- a controller configured to generate the digital calibration code and to generate the analog calibration code responsive to the DC offset.
Dependencies are inferred from the claim text.