Clock frequency drift compensation for a clock generator

An integrated circuit comprising:

• a plurality of clocked circuits;
• a supply voltage input;
• and
• an oscillator circuit configured to provide an output clock signal to the plurality of clocked circuits,
• the oscillator having
• a clock generator configured to generate the output clock signal with a clock frequency,
• wherein the clock generator includes,
• a first variable resistor configured to vary the clock frequency,
• a second variable resistor, and
• a voltage divider having a reference resistor and the second variable resistor,
• wherein the voltage divider is configured to generate a reference stress voltage between the reference resistor and the second variable resistor, and
• a correction feedback block coupled to the clock generator and configured to compare the reference stress voltage to a reference voltage, to adjust a resistance of the first variable resistor, and to adjust a resistance of the second variable resistor in response to the comparing;
• wherein the clock generator further includes,
• a reference voltage divider configured to generate the reference voltage;
• wherein the reference voltage divider includes a second reference resistor matched to the reference resistor and a third reference resistor matched to the reference resistor and configured to approximate a resistance of the first variable resistor.

An oscillator circuit comprising:

• a clock generator configured to generate an output clock signal with a clock frequency;
• wherein the clock generator includes,
• a first variable resistor configured to vary the clock frequency;
• a second variable resistor;
• and
• a voltage divider having a reference resistor and the second variable resistor,
• wherein the voltage divider is configured to generate a reference stress voltage between the reference resistor and the second variable resistor;
• and
• a correction feedback block coupled to the clock generator and configured to compare the reference stress voltage to a reference voltage, to adjust a resistance of the first variable resistor, and to adjust a resistance of the second variable resistor in response to the comparing;
• wherein the first variable resistor is a first resistive digital-to-analog converter (DAC);
• wherein the first resistive DAC is controlled by a first control word and the second variable resistor is a second resistive DAC controlled by a second control word;
• and
• wherein the first control word has more significant bits than the second control word.