PLL lock detector circuit
AssigneeInstituto de Pesquisas Eldorado
InventorsMateus Biancarde Castro, Eduardo Rodrigues de Lima
Life of this patent
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Abstract
A lock-detection circuit designed for integration into a phase-locked loop or a delay-locked loop includes a first signal-duration filter processing an up signal (UP) to generate a filtered UP signal containing segments that exceed a minimum duration, and a second signal-duration filter handling a down signal (DN) to produce a filtered DN signal with segments surpassing the minimum duration. Additionally, the circuit includes first and second timers receiving the filtered signals, and an output logic circuit triggering a LOCK detected signal when both timers are activated. The minimum duration is set to exceed spikes in the UP and DN signals, accounting for jitter, and is longer than the expected duration of a phase error correcting pulse when the loop is in lock.
Claims6
A lock-detection circuit for use in a phase-locked loop or a delay-locked loop, the lock-detection circuit comprising:
- a first signal-duration filter configured to receive an up signal (UP) and to output a filtered UP signal that includes a part of the UP signal that exceeds a minimum duration;
- a second signal-duration filter configured to receive a down signal (a DN signal) and to output a filtered DN signal that includes a part of the DN signal that exceeds the minimum duration;
- a first timer coupled with an output of the first signal-duration filter and configured to receive the filtered UP signal;
- a second timer coupled with an output of the second signal-duration filter and configured to receive the filtered DN signal;
- and
- an output logic circuit with inputs coupled with the first timer and the second timer and configured to assert a LOCK detected signal when both a first timer output and a second timer output are asserted;
- wherein:
- the minimum duration is longer than a spike in the UP signal, including a spike broadened by jitter, and longer than a spike in the DN signal, including a spike broadened by jitter;
- and
- the minimum duration is longer than an expected duration of a phase error correcting pulse when the phase-locked loop or the delay-locked loop is in lock.
A lock detection method that can be used in a phase-locked loop or a delay-locked loop and using an UP signal and a DN signal provided by a phase-frequency detector, the lock detection method comprising:
- receiving the UP signal and the DN signal from the phase-frequency detector;
- filtering the UP signal and the DN signal to suppress signals with a duration shorter than a minimum duration to obtain a filtered UP signal and a filtered DN signal;
- using the filtered UP signal and the filtered DN signal to reset and start a first timer;
- and
- when the first timer has timed out, outputting a LOCK detected signal;
- wherein:
- the minimum duration is longer than a spike in the UP signal, including a spike broadened by jitter, and longer than a spike in the DN signal, including a spike broadened by jitter;
- and
- the minimum duration is longer than an expected duration of a phase error correcting pulse when the phase-locked loop or the delay-locked loop is in lock.
Dependencies are inferred from the claim text.