Decision feedback equalization in semiconductor devices

A memory device comprising:

• a memory interface circuit;
• a memory cell array;
• a data buffer circuit comprising an input buffer and an equalization circuit;
• and
• a control logic circuit coupled to the memory interface circuit, the memory cell array, and the data buffer circuit,
• wherein the equalization circuit comprises:
• a data input port configured to receive data from the input buffer;
• a timing adjustment circuit configured to receive the data from the data input port, wherein the timing adjustment circuit comprises:
• a first path configured to impose a first delay on the data to generate first delayed data, and a second path configured to impose a second delay on the data to generate second delayed data, the first delay being different from the second delay, wherein the first path comprises a first set of one or more inverters, the second path comprises a second set of one or more inverters, and a number of inverters in the first set of one or more inverters is different from a number of inverters in the second set of one or more inverters;
• a first logic circuit configured to receive the first delayed data and the second delayed data and generate a first logic output, wherein the first logic output expands a pulse width corresponding to a first logic value in the data;
• a second logic circuit configured to receive the first delayed data and the second delayed data and generate a second logic output, wherein the second logic output expands a pulse width corresponding to a second logic value in the data;
• a multiplexer configured to select, based on an equalization feedback signal, at least one of (i) the first logic output or (ii) the second logic output, to provide a multiplexer output;
• and
• a data output port configured to output equalized data based on the multiplexer output.

A method for compensating for data distortion from channel loss, the method comprising:

• receiving data from a data input port;
• imposing a first delay on the data to generate first delayed data, and imposing a second delay on the data to generate second delayed data, the first delay being different from the second delay;
• generating, using a first logic circuit, a first logic output based on the first delayed data and the second delayed data, wherein the first logic circuit comprises an OR gate, and wherein the first logic output expands a pulse width corresponding to a first logic value in the data;
• generating, using a second logic circuit, a second logic output based on the first delayed data and the second delayed data, wherein the second logic circuit comprises an AND gate, and wherein the second logic output expands a pulse width corresponding to a second logic value in the data;
• selecting, based on an equalization feedback signal, at least one of (i) the first logic output or (ii) the second logic output, to provide a multiplexer output;
• and
• outputting, at a data output port, equalized data based on the multiplexer output.