Adaptive write current adjustment for persistent memories
AssigneeIntel Corporation
InventorsYuanyuan Li, Rakan Maddah, Prashant S. Damle, Dany-Sebastien Ly-Gagnon, Lunkai Zhang
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Abstract
Systems, apparatuses, and methods provide for technology performs write current adjustment management in crosspoint persistent memory structures. Such technology determines whether to adjust a base current in response to a sampling of write-and-read operations on a set of addresses in a crosspoint persistent memory; determines whether a test current reduces a number of bit fails in response to a determination of whether to adjust the base current; and adjusts the base current based on the test current in response to a determination that the test current reduces the number of bit fails.
Claims18
A memory module comprising:
- a memory array including a plurality of cell blocks in a crosspoint persistent memory;
- and
- a chip controller coupled to the memory array, the chip controller to:
- perform a base sampling of write-and-read operations with a base reset current on a set of addresses in the crosspoint persistent memory;
- determine whether a zero bit error rate for the base sampling exceeds a threshold;
- perform a test sampling of write-and-read operations with a test reset current that is increased relative to the base reset current;
- determine whether the zero bit error rate decreases with the test reset current for the test sampling;
- and
- adjust the base reset current to the test reset current in response to a determination that the test reset current reduces the zero bit error rate.
A computing system comprising:
- a memory array including a plurality of cell blocks in a crosspoint persistent memory;
- and
- a memory controller coupled to the memory array, the memory controller to:
- perform a base sampling of write-and-read operations with a base reset current on a set of addresses in the crosspoint persistent memory;
- determine whether a zero bit error rate for the base sampling exceeds a threshold;
- perform a test sampling of write-and-read operations with a test reset current that is increased relative to the base reset current;
- determine whether the zero bit error rate decreases with the test reset current for the test sampling;
- and
- adjust the base reset current to the test reset current in response to a determination that the test reset current reduces the zero bit error rate.
A method comprising:
- performing a base sampling of write-and-read operations with a base reset current on a set of addresses in a crosspoint persistent memory;
- determining whether a zero bit error rate for the base sampling exceeds a threshold;
- performing a test sampling of write-and-read operations with a test reset current that is increased relative to the base reset current;
- determining whether the zero bit error rate decreases with the test reset current for the test sampling;
- and
- adjusting the base reset current to the test reset current in response to a determination that the test reset current reduces the zero bit error rate.
Dependencies are inferred from the claim text.