Method and apparatus for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory
AssigneeSilicon Motion, Inc.
InventorTsung-Chieh Yang
Life of this patent
Estimating the term…
Abstract
A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.
Claims9
A memory controller for reading data stored in a flash memory, wherein the memory controller is configured to perform the steps of:
- reading a plurality of memory cells of the flash memory by using a first control gate voltage to obtain a first bit sequence from the flash memory;
- reading the plurality of memory cells of the flash memory by using a second control gate voltage to obtain a second bit sequence from the flash memory;
- reading the plurality of memory cells of the flash memory by using a third control gate voltage to obtain a third bit sequence from the flash memory;
- comparing each bit of the first bit sequence with the corresponding bit of the second bit sequence to generate a first comparison result;
- comparing each bit of the first bit sequence with the corresponding bit of the third bit sequence to generate a second comparison result;
- and
- updating the first control gate voltage according to the first comparison result and the second comparison result.
A method for reading data stored in a flash memory, comprising:
- reading a plurality of memory cells of the flash memory by using a first control gate voltage to obtain a first bit sequence from the flash memory;
- reading the plurality of memory cells of the flash memory by using a second control gate voltage to obtain a second bit sequence from the flash memory;
- reading the plurality of memory cells of the flash memory by using a third control gate voltage to obtain a third bit sequence from the flash memory;
- comparing each bit of the first bit sequence with the corresponding bit of the second bit sequence to generate a first comparison result;
- comparing each bit of the first bit sequence with the corresponding bit of the third bit sequence to generate a second comparison result;
- and
- updating the first control gate voltage according to the first comparison result and the second comparison result.
An electronic device, comprising:
- a flash memory;
- and
- a flash memory controller, configured to perform the steps of:
- reading a plurality of memory cells of the flash memory by using a first control gate voltage to obtain a first bit sequence from the flash memory;
- reading the plurality of memory cells of the flash memory by using a second control gate voltage to obtain a second bit sequence from the flash memory;
- reading the plurality of memory cells of the flash memory by using a third control gate voltage to obtain a third bit sequence from the flash memory;
- comparing each bit of the first bit sequence with the corresponding bit of the second bit sequence to generate a first comparison result;
- comparing each bit of the first bit sequence with the corresponding bit of the third bit sequence to generate a second comparison result;
- and
- updating the first control gate voltage according to the first comparison result and the second comparison result.
Dependencies are inferred from the claim text.