Memory device
AssigneeKioxia Corporation
InventorKosuke Hatsuda
Life of this patent
Estimating the term…
Abstract
A memory device includes a first wiring, a second wiring, a memory cell connected between the first wiring and the second wiring, a first power line, a sense amplifier, a current control circuit provided between the first power line and the sense amplifier and including a control terminal connected to a first node, a capacitance element provided between the first node and the second wiring and including a first terminal electrically connected to the second wiring and a second terminal connected to the first node, a second power line, and a first element having an electrical resistance provided between the first node and the second power line.
Claims20
A memory device comprising:
- first wiring;
- second wiring;
- a memory cell connected between the first wiring and the second wiring;
- a first power line;
- a sense amplifier;
- a current control circuit provided between the first power line and the sense amplifier and including a control terminal connected to a first node;
- a capacitance element provided between the first node and the second wiring and including a first terminal electrically connected to the second wiring and a second terminal connected to the first node;
- a second power line;
- and
- a first element having an electrical resistance provided between the first node and the second power line.
A memory device comprising:
- first wiring extending in a first direction;
- second wiring extending in a second direction intersecting the first direction;
- a memory cell connected between the first wiring and the second wiring at a location where the first wiring and the second wiring intersect when viewed in a third direction intersecting the first and second directions;
- a first power line;
- a sense amplifier;
- a current control circuit having a first transistor provided between the first power line and the sense amplifier, the first transistor having a gate connected to a first node;
- a capacitance element provided between the first node and the second wiring and including a first terminal and a second terminal connected to the first node;
- a second power line;
- a first element having an electrical resistance provided between the first node and the second power line;
- and
- a second transistor having a gate connected to the second wiring, a first terminal connected to the first terminal of the capacitance element, and a second terminal connected to ground.
A memory device comprising:
- first wiring;
- second wiring;
- a memory cell connected between the first wiring and the second wiring;
- a first power line;
- a sense amplifier;
- a current control circuit provided between the first power line and the sense amplifier, the current control circuit including a first transistor that is turned on or off to control current flowing between the first power line and the sense amplifier;
- a second power line;
- a first element having an electrical resistance electrically connected between the second power line and a gate of the first transistor;
- and
- a capacitance element electrically connected between the second wiring and the first element and between the second wiring and the gate of the first transistor.
Dependencies are inferred from the claim text.