Display gate driver circuitry with reduced power consumption and smaller footprint

Gate driver circuitry comprising:

• a first gate driver circuit having a first clock terminal configured to receive a first shift register clock signal, a second clock terminal configured to receive a second shift register clock signal different than the first shift register clock signal, and a third clock terminal configured to receive a first output buffer clock signal, wherein the first gate driver circuit further comprises:
• a first p-type silicon transistor having a source-drain terminal configured to receive the first output buffer clock signal;
• a second semiconducting oxide transistor coupled in series with the first p-type silicon transistor;
• a third p-type silicon transistor coupled between a gate terminal of the first p-type silicon transistor and a gate terminal of the second semiconducting oxide transistor;
• a first inverter configured to receive a carry in signal;
• and
• a second inverter coupled to an output of the first inverter and configured to generate a corresponding carry out signal, wherein the third p-type silicon transistor is coupled to an input of the second inverter;
• and
• a second gate driver circuit having a first clock terminal configured to receive the second shift register clock signal, a second clock terminal configured to receive the first shift register clock signal, and a third clock terminal configured to receive a second output buffer clock signal different than the first output buffer clock signal.

A gate driver circuit comprising:

• a first p-type silicon transistor having a source-drain terminal configured to receive an output buffer clock signal;
• a second semiconducting oxide transistor coupled in series with the first p-type silicon transistor;
• a third p-type silicon transistor having a first source-drain terminal coupled to a gate terminal of the first p-type silicon transistor and having a second source-drain terminal coupled to a gate terminal of the second semiconducting oxide transistor;
• a fourth p-type silicon transistor having a source terminal coupled to a first power supply line, a drain terminal on which a carry out signal is produced, and a gate terminal coupled to the second source-drain terminal of the third p-type silicon transistor;
• a fifth semiconducting oxide transistor having a drain terminal coupled to the drain terminal of the fourth p-type silicon transistor, a source terminal coupled to a second power supply line, and a gate terminal shorted to the gate terminal of the fourth p-type silicon transistor;
• a sixth p-type silicon transistor having a source terminal coupled to the first power supply line, a drain terminal coupled to the gate terminal of the fourth p-type silicon transistor, and a gate terminal;
• a seventh semiconducting oxide transistor having a drain terminal coupled to the drain terminal of the sixth p-type silicon transistor, a source terminal coupled to the second power supply line, and a gate terminal coupled to the gate terminal of the sixth p-type silicon transistor;
• an eighth semiconducting oxide transistor having a first source-drain terminal coupled to the gate terminal of the sixth p-type silicon transistor, a second source-drain terminal configured to receive a carry in signal, and a gate terminal configured to receive a first shift register clock signal;
• and
• a ninth p-type silicon transistor having a first source-drain terminal coupled to the gate terminal of the sixth p-type silicon transistor, a second source-drain terminal configured to receive the carry in signal, and a gate terminal configured to receive a second shift register clock signal different than the first shift register clock signal.