Flip-flop circuit and pixel driving circuit

A flip-flop circuit, comprising an input sub-circuit, an AND gate, a control sub-circuit, a duty ratio adjustment sub-circuit, and a reset sub-circuit;

• wherein
• the AND gate comprises a first input terminal, a second input terminal and an output terminal, and is configured to control a clock signal output from the output terminal based on input signals of the first input terminal and the second input terminal of the AND gate, and each clock cycle of the clock signal jumps between a first power supply voltage and a second power supply voltage;
• the input sub-circuit is configured to write the second power supply voltage into at least one of the first input terminal and the second input terminal in response to an input control signal to control the output terminal to output the first power supply voltage or the second power supply voltage;
• the control sub-circuit is configured to control a potential at a first node through the second power supply voltage in response to a data voltage control signal, and the first node is a connection node between the control sub-circuit and the duty ratio adjustment sub-circuit;
• the duty ratio adjustment sub-circuit is configured to control the output terminal to output the first power supply voltage in response to the potential at the first node so as to adjust a duty ratio of the clock signal;
• and
• the reset sub-circuit is configured to respond to a reset signal and reset the potential at the first node through the reset signal.