Non-volatile memories with mixed OxRAM/FeRAM technologies

A data storage circuit comprising a matrix array of memory cells (BCij), of N rows (Li) and M columns (Cj), produced on a semiconductor substrate, comprising:

• for each row (Li), a first input node (WL<i>) configured to receive a selection signal (VWL<i>);
• at least one second input node (SL<j>) configured to receive a first write voltage (VSL<j>);
• for each column (C), an input/output node (BL<j>) configured to receive a second write voltage (VBL<j>) and supply a read voltage (VBL<j>);
• the memory cells (BCij) being configurable and non-volatile;
• each one being intended to operate in either one of two operating configurations (CONF1, CONF2);
• the first operating configuration (CONF1) corresponding to a ferroelectric random-access memory;
• and the second operating configuration (CONF2) corresponding to a metal-oxide resistive random-access memory;
• each memory cell (BCij) comprising:
• a stack of thin layers (NVM) in the following order:
• a first layer (C1) made of an electrically conductive material forming a lower electrode (EL1), a second layer (C2) made of a dielectric and ferroelectric material, a third layer (C3) made of electrically conductive material forming an upper electrode (EL2) connected to the second input node (SL<j>) associated with the column of said memory cell (BCij);
• a selection transistor (T1) having a gate connected to the first input node (WL<i>) associated with the row of said memory cell (BCij) and connecting the lower electrode (EL1) to the input/output node (BL<j>) associated with the column of said memory cell (BCij);
• the data storage circuit being configured, upon each transition from one operating configuration, called starting configuration, to the other operating configuration, called finishing configuration (CONF1, CONF2), to:
• read each memory cell (BCij) in the starting configuration and temporarily store a resulting read signal;
• apply a transformation voltage to each memory cell (BCij);
• convert each read signal in the starting configuration into a write signal compatible with the finishing configuration;
• rewrite each memory cell (BCij) based on the write signals compatible with the starting configuration.