Time multiplexing technique to transform single core processor in a multicore processor
AssigneeSTMicroelectronics International N.V.
InventorAntonio Anastasio
Life of this patent
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Abstract
Disclosed herein a method for transforming a single processor system into an effective multicore system with few modifications to the existing processor. The transformation is achieved by wrapping the processor with a CPU Manager module, which intercepts all CPU transactions, remaps addresses, manages interrupt lines, and controls the CPU clock using clock gating. The transformation to n effective multicore system brings about reduced area and power impacts compared to a full duplication of the whole system, while still reusing the existing program in a multicore environment.
Claims22
A computing system, comprising:
- a physical memory;
- a physical central processing unit (CPU) including a bus arbiter;
- and
- a network-on-chip (NOC) facilitating communication between the physical CPU and the physical memory;
- wherein the physical CPU is configured to be subdivided into a plurality of virtual CPUs and a plurality of virtual CPU managers, with each virtual CPU manager being associated with a corresponding one of the virtual CPUs;
- wherein the bus arbiter is configured to manage communications between the plurality of virtual CPUs and the NOC by routing communications from the NOC to corresponding ones of the virtual CPUs;
- wherein each virtual CPU manager is configured to intercept, dynamically modify, and route transitions on a data bus and an instruction bus of the physical CPU to the virtual CPU associated with that virtual CPU manager;
- and
- wherein each virtual CPU manager is configured to gate clock cycles allocated to its associated virtual CPU during periods when it awaits external data.
A method of dynamically transforming a single-core central processing unit (CPU) into multiple virtual CPUs, the method comprising:
- subdividing a physical CPU connected to a physical memory via a network-on-chip (NOC) into a plurality of virtual CPUs;
- allocating a plurality of virtual CPU managers such each virtual CPU manager is associated with a corresponding one of the virtual CPUs;
- utilizing a bus arbiter within the physical CPU to manage communications between the plurality of virtual CPUs and the NOC, by routing communications from the NOC to corresponding ones of the virtual CPUs;
- intercepting, by each virtual CPU manager, transactions on a data bus and an instruction bus of the physical CPU, and dynamically modifying and routing the intercepted transactions to the virtual CPU associated with that virtual CPU manager;
- and
- gating, by each virtual CPU manager, clock cycles allocated to its associated virtual CPU during periods when it awaits external data.
Dependencies are inferred from the claim text.