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AssigneeIntel Corporation
InventorsSusanne M. Balle, Duane E. Galbi, Andrzej Kuriata, Sundar Nadathur, Nagabhushan Chitlur, Francesc Guim Bernat, Alexander Bachmutsky
Estimating the term…
Methods, apparatus, and software and for hardware microservices accelerated in other processing units (XPUs). The apparatus may be a platform including a System on Chip (SOC) and an XPU, such as a Field Programmable Gate Array (FPGA). The FPGA is configured to implement one or more Hardware (HW) accelerator functions associated with HW microservices. Execution of microservices is split between a software front-end that executes on the SOC and a hardware backend comprising the HW accelerator functions. The software front-end offloads a portion of a microservice and/or associated workload to the HW microservice backend implemented by the accelerator functions. An XPU or FPGA proxy is used to provide the microservice front-ends with shared access to HW accelerator functions, and schedules/multiplexes access to the HW accelerator functions using, e.g., telemetry data generated by the microservice front-ends and/or the HW accelerator functions. The platform may be an infrastructure processing unit (IPU) configured to accelerate infrastructure operations.
A platform comprising:
A method implemented on a platform including a System on Chip (SOC) operatively coupled to a circuit board and communicatively coupled to an other processing unit (XPU) operatively coupled to the circuit board, comprising:
A non-transitory machine-readable medium having software instructions stored thereon configured to be executed on one or more cores on a System on Chip (SOC) in a platform including the SOC and an other processing unit (XPU) communicatively coupled to the SOC, the XPU configured to implement one or more accelerator functions, wherein execution of the instructions on the SOC enables the platform to:
Dependencies are inferred from the claim text.