Streaming scan network latency balancing to reduce cost of testing identical replicated blocks

A processing system comprising:

• one or more memories comprising processor-executable instructions;
• and
• one or more processors configured to execute the processor-executable instructions and cause the processing system to:
• receive, at a programmable block on an integrated circuit, an input numerical value indicating a number of pipeline stages to be used for a test operation in a streaming scan network (SSN) on the integrated circuit;
• select, by the programmable block, based on the input numerical value, a subset of a plurality of pipeline stages in the programmable block using a multiplexer, wherein each pipeline stage of the plurality of pipeline stages comprises a sequential element with a clock, an input, and an output;
• and
• balance latency throughout the SSN on the integrated circuit based on the selected subset of the plurality of pipeline stages in the programmable block.

An apparatus, comprising:

• means for receiving, at a programmable block on an integrated circuit, an input numerical value indicating a number of pipeline stages to be used for a test operation in a streaming scan network (SSN) on the integrated circuit;
• means for selecting, by the programmable block, based on the input numerical value, a subset of a plurality of pipeline stages in the programmable block using a multiplexer, wherein each pipeline stage of the plurality of pipeline stages comprises a sequential element with a clock, an input, and an output;
• and
• means for balancing latency throughout the SSN on the integrated circuit based on the selected subset of the plurality of pipeline stages in the programmable block.