Architecture, system and methods thereof for secure computing using hardware security classifications

A system for secured computing comprising:

• an interconnect;
• a processing element communicatively connected to the interconnect;
• and
• a memory controller communicatively connected to the interconnect and to a memory;
• wherein access of a memory block by the memory controller to and from the interconnect is accompanied by a security class of a plurality of security classes;
• wherein each memory block is associated with a security class assigned to the content stored in the memory block from amongst a plurality of security classes;
• wherein the associated security class of each memory block travels in the system together with the content of the associated memory block;
• wherein the memory controller employs at least one matrix;
• wherein the at least one matrix defines interactions between the security classes of memory blocks of content as the content of the memory blocks which are being handled by at least the memory controller;
• wherein the security classes include i) data classes which are security classes for data and ii) code classes which are security classes for processor instructions;
• and
• wherein the at least one matrix defines:
• i) memory blocks associated with which data classes can be mixed in an operation, as well as determining a result of each such mixing;
• ii) whether code in a memory block associated with a code class can process content of a memory block associated with a specific data class, as well as determining a resulting class for the memory block resulting from the processing when such processing occurs;
• and, iii) whether a memory block associated with one code class can call a memory block associated with another code class.