US 12,645,603 B2Granted

Electronic device and operating method thereof

AssigneeSamsung Electronics Co., Ltd.

InventorsMoongyung Kim, Youngsik Eom, Euiyeon Won, Donghyeon Ham

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Abstract

An electronic device may include: a processor including a first core and a second core, the first core and the second core being configured to execute a process; and a main memory configured to store a page table corresponding to the process. The first core includes: a first translation lookaside buffer (TLB) configured to store a first portion of the page table; a page table walker configured to perform a page table walk operation to look up the page table; and a TLB check predictor configured to store a check weight table and, based on the check weight table, transmit a TLB check request to the second core. The second core includes a second TLB configured to store a second portion of the page table.

Claims14

Dependent claims

An electronic device comprising:

a processor comprising a first core and a second core, the first core and the second core being configured to execute a process;
and
a main memory configured to store a page table corresponding to the process,
wherein the first core comprises:
a first translation lookaside buffer (TLB) configured to store a first portion of the page table;
a page table walker configured to perform a page table walk operation to look up the page table;
and
a TLB check predictor configured to store a check weight table and, based on the check weight table, transmit a TLB check request to the second core,
wherein the second core comprises a second TLB configured to store a second portion of the page table,
wherein the first core is configured to translate a virtual address of the process into a physical address, based on a result of the page table walk operation and a TLB check response received from the second core, and
wherein the check weight table comprises the virtual address and a check weight value corresponding to the virtual address.

8 more elements

An operating method of an electronic device comprising a first core, a second core, and a main memory configured to execute processes, wherein the main memory comprises a page table, the first core comprises a first TLB configured to store a first portion of the page table, and the second core comprises a second TLB comprising a second portion of the page table, the operating method comprising:

looking up the first TLB, performed by the first core, based on a virtual address of a process;
looking up the page table, based on a result of the looking up the first TLB, by the first core;
performing an operation of looking up the second TLB, based on the result of the looking up the first TLB and a check weight table;
and
translating the virtual address into a physical address, based on a result of the looking up the page table and a TLB check response received from the second core, by the first core,
wherein the check weight table comprises the virtual address and a check weight value corresponding to the virtual address.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/972,375Filed 6 Dec 2024
Priority: KR 10-2024-005354522 Apr 2024
Published: US 2025/0328476 A123 Oct 2025
Granted: 2 Jun 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 12/1027
Address translation: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 12/1036
Using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]: for multiple virtual address spaces,…
G06F 12/1009
Address translation: using page tables, e.g. page table structures
G06F 2212/1024
Performance improvement: latency reduction