Allocation of spare cache reserved during non-speculative execution and speculative execution

A system, comprising:

• a plurality of cache sets;
• a logic circuit coupled to the plurality of cache sets and configured to:
• allocate a first subset of the plurality of cache sets to cache data accessed by at least one processor, during execution of first instructions in the at least one processor;
• allocate a second subset of the plurality of cache sets to cache data accessed by the at least one processor, during execution of second instructions in the at least one processor before a result of the execution of the first instructions indicate whether execution of the second instructions is required;
• reserve at least one other cache set of the plurality of cache sets during a time period in which the execution of the second instructions and the execution of the first instructions are performed, wherein the at least one other cache set differs from the first subset and the second subset;
• a plurality of cache set registers associated with the plurality of cache sets, respectively, wherein the logic circuit is configured to allocate and reconfigure subsets of the plurality of cache sets using the plurality of cache set registers;
• wherein the first subset of the plurality of cache sets comprises a first cache set, the second subset of the plurality of cache sets comprises a second cache set, and the at least one other cache set comprises a third cache set;
• and wherein the plurality of cache set registers comprises:
• a first cache set register associated with the first cache set, configured to store a first cache set index configured to indicate allocation of the first cache set in a non-speculative mode;
• a second cache set register associated with the second cache set, configured to store a second cache set index configured to indicate allocation of the second cache set in a speculative mode;
• and
• a third cache set register associated with the third cache set, configured to store a third cache set index configured to indicate allocation of the third cache set as a spare cache set;
• wherein the logic circuit is further configured to:
• generate a set index based on i) a memory address received and ii) identification of the speculative mode or the non-speculative mode received from the processor identifying execution type;
• and
• determine whether the set index matches with content stored in the first cache set register, the second cache set register, or the third cache set register.