Device and method with cache coherency maintenance for PIM operations
AssigneeSamsung Electronics Co., Ltd.
InventorsYuhwan Ro, Hyunsoo Kim
Life of this patent
Estimating the term…
Abstract
Disclosed are an electronic device for maintaining the cache coherency of data related to a processing-in-memory (PIM) operation, a processor, and an operating method of the electronic device. The electronic device includes: a processor configured to, when processing an instruction causing a processing-in-memory (PIM) operation, selectively target, for movement from a cache to a memory, data related to the PIM operation that is stored in the cache; and the memory configured to, based on the targeting of the data for movement from the cache to the memory, receive the data from the cache, and perform the PIM operation on the data in the memory based on a command corresponding to the instruction that is relayed from the processor.
Claims19
An electronic device comprising:
- a processor configured to, when processing an instruction causing a processing-in-memory (PIM) operation, selectively target, for movement from a cache to a memory, data related to the PIM operation that is stored in the cache;
- and
- the memory configured to, based on the targeting of the data for movement from the cache to the memory, receive the data from the cache, and perform the PIM operation on the data in the memory based on a command corresponding to the instruction that is relayed from the processor,
- wherein the processor comprises:
- a core including:
- a PIM instruction detector configured to determine whether the instruction to be executed in the process PIM operation and transmit an address of data related to the PIM operation to a cache flush request generator based on determining that the instruction to be executed causes a PIM operation;
- and
- the cache flush request generator configured to generate a cache flush request comprising the address of the data related to the PIM operation and transmit the cache flush request to the cache;
- and
- a memory controller configured to transmit the data related to the PIM operation based on the cache flush request from the cache to the memory.
A processor comprising:
- a core configured to determine that an operation caused by execution of an instruction to be executed in the processor is a PIM type of operation and based thereon transmit, to a cache, a move request including an address of data related to the PIM operation;
- the cache configured to, based on the move request, transmit, to a memory controller, a write request for writing the data to the memory;
- and
- the memory controller configured to transmit a write command to the memory based on the write request received from the cache, to transfer data related to the PIM operation from the cache to the memory.
A method of operating an electronic device comprising a processor and a memory, the method comprising:
- moving data determined to be related to a PIM operation stored in a cache to the memory when processing, in the processor, an instruction causing the PIM operation to be performed in the memory;
- receiving the data moved from the cache into the memory;
- and
- based on the instruction relayed from the processor, performing, by the memory, the PIM operation on the data in the memory,
- wherein the moving comprises:
- determining whether the instruction to be executed in the processor causes a PIM operation and transmit an address of data related to the PIM operation to a cache flush request generator based on determining that the instruction to be executed causes a PIM operation;
- generating a cache ush request comprising the address of the data related to the PIM operation and transmit the cache flush request to the cache;
- and
- transmitting the data related to the PIM operation based on the cache flush request from the cache to the memory.
Dependencies are inferred from the claim text.