Half latch level shifting circuit for non-volatile memory architectures

A memory device comprising:

• controller circuitry to generate low voltage (LV) addressing signals and a LV partition enable signal;
• a plurality of memory partitions coupled to the controller circuitry, each partition comprising:
• level shifter circuitry to receive the LV partition enable signal from the controller circuitry and output a high voltage (HV) enable signal and a LV enable signal based on the LV partition enable signal;
• a plurality of half latch circuits coupled to the level shifter circuitry, the half latch circuits to generate HV addressing signals based on the HV enable signal, the LV enable signal, and the LV addressing signals generated by the controller circuitry, each half latch circuit comprising a transistor connected between the output of the half latch circuit and an input to a cascaded inverter circuit of the half latch circuit, a gate of the transistor connected to a bias voltage.

A memory device comprising:

• controller circuitry to generate first and second low voltage (LV) addressing signals and a LV block select signal;
• a plurality of memory partitions coupled to the controller circuitry, each partition comprising:
• a plurality of level shifter circuits to receive the LV block select signal from the controller circuitry and output a high voltage (HV) select signal and a LV select signal based on the LV block select signal;
• a plurality of half latch circuits, wherein subsets of the plurality of half latch circuits are connected to respective level shifter circuits, each half latch circuit to generate HV addressing signals based on the HV select signal, the LV select signal, and the LV addressing signals generated by the controller circuitry, each half latch circuit comprising a transistor connected between the output of the half latch circuit and an input to a cascaded inverter circuit of the half latch circuit, a gate of the transistor connected to a bias voltage.