Synchronized request handling at a memory device
AssigneeMicron Technology, Inc.
InventorsTony M. Brewer, Dean E. Walker
Life of this patent
Estimating the term…
Abstract
System and techniques for synchronized request handling at a memory device are described herein. A request is received at the memory device. Here, the request indicates a memory address corresponding to a set of cache lines and a single cache line in the set of cache lines. The memory device maintains a deferred list for the set of cache lines and a set of lists with each member of the set of lists corresponding to one cache line in the set of cache lines. The memory device tests the deferred list to determine that the deferred list is not empty and places the request in the deferred list.
Claims20
A cache device comprising:
- a first interface configured to receive a memory requests;
- a second interface configured to communicate with a memory device;
- a storage device with a portion configured as a set of cache lines including a cache line;
- and
- processing circuitry configured to:
- maintain a tag state for the cache line;
- maintain a set of lists for the set of cache lines including a list for the cache line;
- maintain a deferred list for the set of cache lines;
- receive, via the first interface, a memory request for the cache line;
- and
- handle the memory request based on a sequence of determining if the deferred list is empty, if the list for the cache line is empty, or the tag state indicates that the cache line is busy.
Dependencies are inferred from the claim text.