US 12,645,577 B2Granted

Memory device with a die having multiple pseudo channels per channel

AssigneeMicron Technology, Inc.

InventorSujeet Ayyapureddi

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Abstract

A memory device (e.g., a high-bandwidth (HBM) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. The memory die can include first memory banks associated with a first channel (e.g., having a first command address (CA) bus) and a first pseudo channel (e.g., having a first data (DQ) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second DQ bus). Operations can be performed at the first memory banks or the second memory banks in response to a command received through the first CA bus. The operations can cause data to be returned to circuitry that routes the data to an interface to the first DQ bus or an interface to the second DQ bus based on whether the data resulted from operations at the first memory banks or the second memory banks.

Claims21

Dependent claims

A high-bandwidth memory (HBM) device comprising:

a plurality of channels each associated with a command address bus, each channel subdivided into a plurality of pseudo channels each associated with a data bus;
a plurality of memory dies, a memory die of the plurality of memory dies comprising:
an interface to a command address bus associated with a first channel;
an interface to a first data bus associated with a first pseudo channel of the first channel;
an interface to a second data bus associated with a second pseudo channel of the first channel;
first memory banks associated with the first pseudo channel of a first channel;
second memory banks associated with the second pseudo channel of the first channel;
and
control circuitry configured to:
responsive to a determination that first return data is received at the control circuitry from the first memory banks in response to performing first operations at one or more of the first memory banks, provide the first return data to the interface to the first data bus, wherein the first operations are associated with a first command received via the command address bus.

7 more elements

A memory device comprising:

a memory die including:
an interface to a first data bus of the memory device;
an interface to a second data bus of the memory device;
an interface to a command address bus of the memory die;
one or more first memory banks coupled with the interface to the command address bus and associated with the first data bus;
one or more second memory banks coupled with the interface to the command address bus and associated with the second data bus;
and
circuitry configured to:
receive return data responsive to performing operations at the one or more first memory banks or the one or more second memory banks, the operations associated with a command received from the command address bus;
determine whether the return data is received in response to performing the operations at the one or more first memory banks or the one or more second memory banks;
responsive to the determination that the return data is received in response to performing the operations at the one or more first memory banks, provide the return data to the interface to the first data bus;
and
responsive to the determination that the return data is received in response to performing the operations at the one or more second memory banks, provide the return data to the interface to the second data bus.

10 more elements

A method comprising:

receiving, from a command address bus coupled with one or more first memory banks associated with a first data bus and one or more second memory banks associated with a second data bus, a command to perform operations at the one or more first memory banks or the one or more second memory banks, the one or more first memory banks and the one or more second memory banks located on a memory die;
responsive to receiving the command, determining whether the command is targeted to the one or more first memory banks or the one or more second memory banks;
responsive to the determination that the command is targeted to the one or more first memory banks, performing the operations at the one or more first memory banks;
responsive to the determination that the command is targeted to the one or more second memory banks, performing the operations at the one or more first memory banks;
responsive to performing the operations at the one or more first memory banks or the one or more second memory banks, receiving return data;
determining whether the return data is received in response to performing the operations at the one or more first memory banks or the one or more second memory banks;
responsive to the determination that the return data is received in response to performing the operations at the one or more first memory banks, providing the return data to the first data bus;
and
responsive to the determination that the return data is received in response to performing the operations at the one or more second memory banks, providing the return data to the second data bus.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/790,391Filed 31 Jul 2024 · us provisional application
Priority: 14 Aug 2023
Published: US 2025/0061070 A120 Feb 2025
Granted: 2 Jun 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 12/0223
Addressing or allocation; Relocation: user address space allocation, e.g. contiguous or non contiguous base addressing
G06F 13/1647
Based on arbitration: with interleaved bank access
G06F 13/1678
Details of memory controller: using bus width
G06F 13/1684
Details of memory controller: using multiple buses