Debugging communication among units on processor simulator

A computer program product, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to perform a method comprising:

• identifying a data transfer mismatch between a sender and a receiver from among a plurality of units of a software simulator of a hardware processor lacking data-dependent conditional branch support, wherein the software simulator runs the plurality of the units which communicate with each other via First-In First-Outs (FIFOs) by:
• counting, by the hardware processor, amounts of data the sender writes to the FIFOs and amounts of data the receiver reads from the FIFOs for a given data transfer, the amounts of data the sender writes to the FIFOs and the amounts of data the receiver reads from the FIFOs being known prior to execution time;
• avoiding blocking, by the hardware processor, during reading and writing operations with respect to the FIFOs by (i) reading dummy data by the receiver, even if the FIFOs are empty, when the receiver tries reading from the FIFOs, and (ii) discarding written data if the FIFOs are full, when the sender tries writing to the FIFOs;
• and
• identifying, by the hardware processor, mismatches in the amounts of data the sender writes to the FIFOs versus the amounts of data the receiver reads from the FIFOs for the given data transfer;
• and
• performing a corrective action including updating an instruction set architecture in response to the mismatches in the amounts of data.

A computer processing system comprising:

• a memory device storing program code;
• and
• a processor device, operatively coupled to the memory device, for running the program code to:
• identify a data transfer mismatch between a sender and a receiver from among a plurality of units of a software simulator of a hardware processor lacking data-dependent conditional branch support, wherein the software simulator runs the plurality of the units which communicate with each other via First-In First-Outs (FIFOs), by having the processor device:
• count amounts of data the sender writes to the FIFOs and amounts of data the receiver reads from the FIFOs for a given data transfer, the amounts of data the sender writes to the FIFOs and the amounts of data the receiver reads from the FIFOs being known prior to execution time;
• avoid blocking during reading and writing operations with respect to the FIFOs by (i) reading dummy data by the receiver, even if the FIFOs are empty, when the receiver tries reading from the FIFOs, and (ii) discarding written data if the FIFOs are full, when the sender tries writing to the FIFOs;
• and
• identify mismatches in the amounts of data the sender writes to the FIFOs versus the amounts of data the receiver reads from the FIFOs for the given data transfer;
• and
• perform a corrective action including updating an instruction set architecture in response to the mismatches in the amounts of data.