Memory apparatus configured with scrubbing or refreshing operations to preserve integrity of stored data and method for operating the same

A memory apparatus, comprising:

• a memory array comprising memory cells;
• an error correction code (ECC) engine in electronic communication with the memory array;
• a memory controller in electronic communication with the ECC engine, the memory controller operable to cause, in response to a read command, the memory apparatus to:
• perform a read operation on a set of memory cells;
• detect an error in data read from the set of memory cells based on an error correction code (ECC) operation performed on the data by the ECC engine;
• and
• perform a further operation on the set of memory cells according to a detecting result responsive to the read operation, wherein at least a portion of the further operation is performed in parallel with transmission of a response to the read command over a data bus.

A memory apparatus, comprising:

• a memory array comprising memory cells and operable to perform a read operation on a set of memory cells in response to a read command;
• an error correction code (ECC) engine coupled with the memory array and operable to detect an error in data read from the set of memory cells based on an ECC operation performed on the data;
• and
• circuitry coupled with the ECC engine and operable to perform, in response to the read command, a further operation on the set of memory cells according to a detecting result responsive to the read operation, wherein the further operation is performed following the ECC operation and performed at least in part before end of transmission of a response to the read command.