US 12,645,528 B2 · Single signal debug port

Abstract

According to an embodiment, a system is provided that includes a debugging tool and an application board. The debugging tool includes a serial wire debug (SWD) host coupled to a single signal debug port (SSDP) host. The application board includes an SWD target coupled to an SSDP target. The SWD target is configured to communicate SWD signals with the SWD host. The SSDP target is configured to encode the SWD signals to SSDP signals for communication over a Controller Area Network (CAN) Bus between the application board and the debugging tool. The SSDP signals are pulse-width modulation (PWM) encoded signals of the SWD signals. An SWD clock signal generated by the SWD host is the carrier signal for the PWM encoded signals. The SSDP target is configured to decode the SSDP signals received from the SSDP host over the CAN Bus to the SWD signals.

Claims20

Dependent claims

A first circuit for communicating serial wire debug (SWD) signals over a Controller Area Network (CAN) Bus, the first circuit comprising:

a non-transitory memory storage comprising instructions;
and
a processor in communication with the non-transitory memory storage, wherein the instructions, when executed by the processor, cause the processor to:
transmit an activation sequence comprising a consecutive set number of logic high pulse-width modulation (PWM) signals or multiple CAN messages having errors over the CAN Bus, the transmitting resulting in CAN nodes coupled to the first circuit via the CAN Bus to transition to a Bus-OFF state, and
receive a response sequence over the CAN Bus from a second circuit coupled to the first circuit upon successful activation of the activation sequence, the response sequence comprising a signal pattern of “0000_1111_0000_1111_0000_11” followed by a frequency period value of the last cycle of the activation sequence.

2 more elements

A first circuit for communicating serial wire debug (SWD) signals over a Controller Area Network (CAN) Bus, the first circuit comprising:

a non-transitory memory storage comprising instructions;
and
a processor in communication with the non-transitory memory storage, wherein the instructions, when executed by the processor, cause the processor to:
receive an activation sequence from a second circuit, the activation sequence comprising a consecutive set number of logic high pulse-width modulation (PWM) signals or multiple CAN messages having errors over the CAN Bus, the activation sequence resulting in CAN nodes coupled to the second circuit via the CAN Bus to transition to a Bus-OFF state, and
transmit a response sequence over the CAN Bus to the second circuit coupled to the first circuit upon successful activation of the activation sequence, the response sequence comprising a signal pattern of “0000_1111_0000_1111_0000_11” followed by a frequency period value of the last cycle of the activation sequence.

2 more elements

A method for communicating serial wire debug (SWD) signals over a Controller Area Network (CAN) Bus, comprising:

communicating, between a first circuit and a second circuit over the CAN Bus, an activation sequence comprising a consecutive set number of logic high pulse-width modulation (PWM) signals or multiple CAN messages having errors over the CAN Bus, the communicating resulting in CAN nodes coupled to the first circuit via the CAN Bus to transition to a Bus-OFF state;
and
communicating, between the first circuit and the second circuit over the CAN Bus, a response sequence upon successful activation of the activation sequence, the response sequence comprising a signal pattern of “0000_1111_0000_1111_0000_11” followed by a frequency period value of the last cycle of the activation sequence.

Dependencies are inferred from the claim text.

Single signal debug port

Life of this patent

Single signal debug port

Life of this patent

Abstract

Claims20