Operation cache
AssigneeAdvanced Micro Devices, Inc.
InventorDavid N. Suggs
Life of this patent
Estimating the term…
Abstract
A system and method for using an operation (op) cache is disclosed. The system and method include an op cache for caching previously decoded instructions. The op cache includes a plurality of physically indexed and tagged instructions allowing sharing of instructions between threads. The op cache is chained through multiple ways allowing service of a plurality of instructions in a cache line. The op cache is stored between a shared operation storage and immediate/displacement storage to maximize capacity.
Claims18
An operation cache (OC), the OC comprising:
- a memory that stores at least one physically indexed and tagged decoded instruction, wherein the tagged decoded instruction is associated with physical address bits of the instruction in an instruction cache;
- wherein the at least one physically indexed and tagged decoded instruction is added to the cache based on a build qualifier using a tag miss corresponding to an access count of zero and a tag hit corresponding to an access count of one,
- wherein the at least one physically indexed and tagged decoded instruction is stored in a fixed width format to eliminate determining instruction boundaries, and
- wherein the OC allows for sharing between threads and selection of the physically indexed and tagged decoded instruction.
A method for caching in an operation cache (OC), the method comprising:
- physically indexing and tagging at least one decoded instruction to form a physically indexed and tagged decoded instruction, wherein the tagged decoded instruction is associated with physical address bits of the instruction in an instruction cache;
- adding the physically indexed and tagged decoded instruction to the OC based on a build qualifier using a tag miss corresponding to an access count of zero and a tag hit corresponding to an access count of one wherein the physically indexed and tagged decoded instruction is stored in a fixed width format to eliminate determining instruction boundaries;
- and
- utilizing the OC to share between threads and select the physically indexed and tagged decoded instruction.
A non-transitory computer readable storage medium storing program instructions, wherein the program instructions provide information used during a semiconductor fabrication process to produce circuitry, the circuitry comprising:
- an operation cache (OC) comprising a memory, the OC adapted to store at least one physically indexed and tagged decoded instruction shared between threads;
- circuitry configured to physically index and tag at least one decoded instruction to form the physically indexed and tagged decoded instruction wherein the tagged decoded instruction is associated with the physical address bits of instruction in an instruction cache;
- circuitry configured to add the physically indexed and tagged decoded instruction to the OC based on a build qualifier using a tag miss corresponding to an access count of zero and a tag hit corresponding to an access count of one, wherein the at least one physically indexed and tagged decoded instruction is stored in a fixed width format to eliminate determining instruction boundaries;
- and
- circuitry configured to utilize the OC to share between threads and select the physically indexed and tagged decoded instruction.
Dependencies are inferred from the claim text.